Patents by Inventor Srikanth Manian
Srikanth Manian has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240136977Abstract: A driver includes an operational amplifier which includes a first amplifier input coupled to a first driver input, a second amplifier input coupled to a second driver input, a first amplifier output, a second amplifier output, a third amplifier output and a fourth amplifier output. The first amplifier output is coupled to the first driver output and the third amplifier output is coupled to the second driver output in a voltage-mode operation. The second amplifier output is coupled to the first driver output and the fourth amplifier output is coupled to the second driver output in a current-mode operation.Type: ApplicationFiled: October 23, 2022Publication date: April 25, 2024Inventors: Srikanth Manian, Sumantra Seth, Trilok Kamagond
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Publication number: 20230318587Abstract: A serial bus re-driver circuit includes an edge detector circuit and a booster circuit. The edge detector circuit is configured to detect a transition of serial bus signal. The booster circuit is coupled to the edge detector circuit, and is configured to switch current to the serial bus signal. The booster circuit includes a leading edge boost pulse generation circuit and a trailing edge boost pulse generation circuit. The leading edge boost pulse generation circuit is configured to switch a first current pulse to the serial bus signal at the transition of the serial bus signal. The trailing edge boost pulse generation circuit is configured to switch a second current pulse to the serial bus signal. The second current pulse is shorter than the first current pulse.Type: ApplicationFiled: June 6, 2023Publication date: October 5, 2023Inventors: Srijan RASTOGI, Srikanth MANIAN
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Patent number: 11711072Abstract: A serial bus re-driver circuit includes an edge detector circuit and a booster circuit. The edge detector circuit is configured to detect a transition of serial bus signal. The booster circuit is coupled to the edge detector circuit, and is configured to switch current to the serial bus signal. The booster circuit includes a leading edge boost pulse generation circuit and a trailing edge boost pulse generation circuit. The leading edge boost pulse generation circuit is configured to switch a first current pulse to the serial bus signal at the transition of the serial bus signal. The trailing edge boost pulse generation circuit is configured to switch a second current pulse to the serial bus signal. The second current pulse is shorter than the first current pulse.Type: GrantFiled: June 18, 2020Date of Patent: July 25, 2023Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Srijan Rastogi, Srikanth Manian
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Patent number: 11509266Abstract: A system includes a data path and a phase-locked loop (PLL) coupled to the data path. The system also includes a voltage-controlled oscillator (VCO) coupled to the PLL. The VCO includes an LC circuit with first and second differential output terminals. The VCO also includes a first resistor coupled between the first differential output terminal and drain terminals of a first pair of complementary metal-oxide semiconductor (CMOS) transistors. The VCO also includes a second resistor coupled between the second differential output terminal and drain terminals of a second pair of CMOS transistors.Type: GrantFiled: October 5, 2021Date of Patent: November 22, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Srinivas Theertham, Srikanth Manian, Uday Kiran Meda
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Publication number: 20220038056Abstract: A system includes a data path and a phase-locked loop (PLL) coupled to the data path. The system also includes a voltage-controlled oscillator (VCO) coupled to the PLL. The VCO includes an LC circuit with first and second differential output terminals. The VCO also includes a first resistor coupled between the first differential output terminal and drain terminals of a first pair of complementary metal-oxide semiconductor (CMOS) transistors. The VCO also includes a second resistor coupled between the second differential output terminal and drain terminals of a second pair of CMOS transistors.Type: ApplicationFiled: October 5, 2021Publication date: February 3, 2022Inventors: Srinivas THEERTHAM, Srikanth MANIAN, Uday Kiran MEDA
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Patent number: 11171601Abstract: A system includes a data path and a phase-locked loop (PLL) coupled to the data path. The system also includes a voltage-controlled oscillator (VCO) coupled to the PLL. The VCO includes an LC circuit with first and second differential output terminals. The VCO also includes a first resistor coupled between the first differential output terminal and drain terminals of a first pair of complementary metal-oxide semiconductor (CMOS) transistors. The VCO also includes a second resistor coupled between the second differential output terminal and drain terminals of a second pair of CMOS transistors.Type: GrantFiled: July 29, 2020Date of Patent: November 9, 2021Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Srinivas Theertham, Srikanth Manian, Uday Kiran Meda
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Publication number: 20210119619Abstract: A serial bus re-driver circuit includes an edge detector circuit and a booster circuit. The edge detector circuit is configured to detect a transition of serial bus signal. The booster circuit is coupled to the edge detector circuit, and is configured to switch current to the serial bus signal. The booster circuit includes a leading edge boost pulse generation circuit and a trailing edge boost pulse generation circuit. The leading edge boost pulse generation circuit is configured to switch a first current pulse to the serial bus signal at the transition of the serial bus signal. The trailing edge boost pulse generation circuit is configured to switch a second current pulse to the serial bus signal. The second current pulse is shorter than the first current pulse.Type: ApplicationFiled: June 18, 2020Publication date: April 22, 2021Inventors: Srijan Rastogi, Srikanth Manian
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Patent number: 10924309Abstract: A receiver circuit includes a quadrature signal generator to generate an in-phase (I) signal and a quadrature (Q) signal from a local oscillator signal and an IQ phase sense and control circuit to generate a phase adjustment code responsive to a phase error between quadrature signals generated by a plurality of mixers. The receiver circuit also includes a phase corrector to adjust a phase difference between the I and Q signals from the quadrature signal generator to generate corrected I and Q signals to be provided to the plurality of mixers.Type: GrantFiled: February 18, 2020Date of Patent: February 16, 2021Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Yogesh Darwhekar, Pranav Kumar, Arpan Thakkar, Naveen Mahadev, Srikanth Manian
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Publication number: 20200186403Abstract: A receiver circuit includes a quadrature signal generator to generate an in-phase (I) signal and a quadrature (Q) signal from a local oscillator signal and an IQ phase sense and control circuit to generate a phase adjustment code responsive to a phase error between quadrature signals generated by a plurality of mixers. The receiver circuit also includes a phase corrector to adjust a phase difference between the I and Q signals from the quadrature signal generator to generate corrected I and Q signals to be provided to the plurality of mixers.Type: ApplicationFiled: February 18, 2020Publication date: June 11, 2020Inventors: Yogesh DARWHEKAR, Pranav KUMAR, Arpan THAKKAR, Naveen MAHADEV, Srikanth MANIAN
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Patent number: 10608853Abstract: A receiver circuit includes a quadrature signal generator to generate an in-phase (I) signal and a quadrature (Q) signal from a local oscillator signal and an IQ phase sense and control circuit to generate a phase adjustment code responsive to a phase error between quadrature signals generated by a plurality of mixers. The receiver circuit also includes a phase corrector to adjust a phase difference between the I and Q signals from the quadrature signal generator to generate corrected I and Q signals to be provided to the plurality of mixers.Type: GrantFiled: September 13, 2018Date of Patent: March 31, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Yogesh Darwhekar, Pranav Kumar, Arpan Thakkar, Naveen Mahadev, Srikanth Manian
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Publication number: 20200092148Abstract: A receiver circuit includes a quadrature signal generator to generate an in-phase (I) signal and a quadrature (Q) signal from a local oscillator signal and an IQ phase sense and control circuit to generate a phase adjustment code responsive to a phase error between quadrature signals generated by a plurality of mixers. The receiver circuit also includes a phase corrector to adjust a phase difference between the I and Q signals from the quadrature signal generator to generate corrected I and Q signals to be provided to the plurality of mixers.Type: ApplicationFiled: September 13, 2018Publication date: March 19, 2020Inventors: Yogesh DARWHEKAR, Pranav KUMAR, Arpan THAKKAR, Naveen MAHADEV, Srikanth MANIAN
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Patent number: 10250248Abstract: In some embodiments, an apparatus comprises a device clock configured to generate a device clock signal a synchronization (SYSREF) clock generation circuit configured to receive the device clock signal from the device clock. The SYSREF clock generating circuit comprises a SYSREF divider configured to generate a SYSREF clock at least partially according to the device clock signal, an interpolator configured to generate a shifted clock at least partially according to the device clock signal, and a latch coupled to the SYSREF divider and the interpolator and configured to sample the SYSREF clock at a rising edge of the shifted clock.Type: GrantFiled: August 8, 2018Date of Patent: April 2, 2019Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Srikanth Manian, Srinivas Theertham, Jagdish Chand, Dinesh Jain
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Patent number: 10243573Abstract: Frequency synthesis is based on phase synchronizing PLL output across REFERENCE and VCO clock domains (including outputs for multiple PLLs), based on an input (REF-Domain) SYNC signal (phase timing reference). A frequency synthesizer includes a VCO to generate VCO_clk and a PLL output circuit, such as a channel divider, to generate PLL_OUT based on VCO_clk (in the VCO-Domain). The VCO loop includes a PD to phase compare an input PD_clock based on REF_CLK, and a VCO feedback signal based on divided VCO_clk (NDIV_out). SYNC alignment circuitry generates a SYNC alignment signal based on SYNC, PD_clk, and NDIV_out (REF-Domain), which is used to synchronize the PLL output circuit and PLL_OUT to SYNC. If a reference divider generates PD_clk, the SYNC alignment circuitry generates a reset to SYNC-align the reference divider. If the VCO loop uses fractional divide, the SYNC alignment circuitry resets the fractional modulator to a known sequence.Type: GrantFiled: April 23, 2018Date of Patent: March 26, 2019Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Jagdish Chand Goyal, Peeyoosh Mirajkar, Shankaranarayana Karantha, Ashwin Ravisankar, Srikanth Manian, Srinivas Theertham
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Publication number: 20180351541Abstract: In some embodiments, an apparatus comprises a device clock configured to generate a device clock signal a synchronization (SYSREF) clock generation circuit configured to receive the device clock signal from the device clock. The SYSREF clock generating circuit comprises a SYSREF divider configured to generate a SYSREF clock at least partially according to the device clock signal, an interpolator configured to generate a shifted clock at least partially according to the device clock signal, and a latch coupled to the SYSREF divider and the interpolator and configured to sample the SYSREF clock at a rising edge of the shifted clock.Type: ApplicationFiled: August 8, 2018Publication date: December 6, 2018Inventors: Srikanth Manian, Srinivas Theertham, Jagdish Chand, Dinesh Jain
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Patent number: 10075156Abstract: In some embodiments, an apparatus comprises a device clock configured to generate a device clock signal a synchronization (SYSREF) clock generation circuit configured to receive the device clock signal from the device clock. The SYSREF clock generating circuit comprises a SYSREF divider configured to generate a SYSREF clock at least partially according to the device clock signal, an interpolator configured to generate a shifted clock at least partially according to the device clock signal, and a latch coupled to the SYSREF divider and the interpolator and configured to sample the SYSREF clock at a rising edge of the shifted clock.Type: GrantFiled: August 9, 2017Date of Patent: September 11, 2018Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Srikanth Manian, Srinivas Theertham, Jagdish Chand, Dinesh Jain
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Patent number: 9954705Abstract: The disclosure provides a frequency synthesizer. It includes a PFD that generates an up signal and a down signal in response to a reference signal and a feedback signal. A charge pump generates a control voltage in response to the up signal and the down signal. A low pass filter generates a filtered voltage in response to the control voltage. An oscillator circuit generates an output signal in response to the filtered voltage. A feedback divider is coupled between the oscillator circuit and the PFD, and divides the output signal by a first integer divider to generate the feedback signal. A sigma delta modulator (SDM) generates a second integer divider in response to the feedback signal, the reference signal, the output signal and the first integer divider. A digital filter is coupled between the SDM and the feedback divider, and filters quantization noise associated with the SDM.Type: GrantFiled: December 22, 2016Date of Patent: April 24, 2018Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Yogesh Darwhekar, Srikanth Manian, Srinivas Theertham, Jagdish Chand Goyal, Robert Karl Butler
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Publication number: 20180097512Abstract: In some embodiments, an apparatus comprises a device clock configured to generate a device clock signal a synchronization (SYSREF) clock generation circuit configured to receive the device clock signal from the device clock. The SYSREF clock generating circuit comprises a SYSREF divider configured to generate a SYSREF clock at least partially according to the device clock signal, an interpolator configured to generate a shifted clock at least partially according to the device clock signal, and a latch coupled to the SYSREF divider and the interpolator and configured to sample the SYSREF clock at a rising edge of the shifted clock.Type: ApplicationFiled: August 9, 2017Publication date: April 5, 2018Inventors: Srikanth MANIAN, Srinivas THEERTHAM, Jagdish CHAND, Dinesh JAIN
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Patent number: 9762292Abstract: A method of charging a power harvested supply in an electronic communication device, which can be an NFC (near field communication) device. The power harvested supply in the electronic communication device is charged without causing dV/V violation and avoids false wake up. An RF (radio frequency) field is received at the antenna of the electronic communication device. A differential voltage is generated from the RF field at a first tag pin and a second tag pin of the electronic communication device. A bandgap reference voltage and a reference current are generated in response to the differential voltage. A shunt current is generated in response to the differential voltage and the bandgap reference voltage. A bank of switching devices is activated if the shunt current is more than the reference current.Type: GrantFiled: September 27, 2013Date of Patent: September 12, 2017Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Srikanth Manian, Yogesh Darwhekar, Abhishek Agrawal, Koby Levy, Yaniv Tzoreff, Erez Shalom
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Publication number: 20170187515Abstract: The disclosure provides a frequency synthesizer. It includes a PFD that generates an up signal and a down signal in response to a reference signal and a feedback signal. A charge pump generates a control voltage in response to the up signal and the down signal. A low pass filter generates a filtered voltage in response to the control voltage. An oscillator circuit generates an output signal in response to the filtered voltage. A feedback divider is coupled between the oscillator circuit and the PFD, and divides the output signal by a first integer divider to generate the feedback signal. A sigma delta modulator (SDM) generates a second integer divider in response to the feedback signal, the reference signal, the output signal and the first integer divider. A digital filter is coupled between the SDM and the feedback divider, and filters quantization noise associated with the SDM.Type: ApplicationFiled: December 22, 2016Publication date: June 29, 2017Inventors: Yogesh Darwhekar, Srikanth Manian, Srinivas Theertham, Jagdish Chand Goyal, Robert Karl Butler
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Frequency synthesizer for achieving fast re-lock between alternate frequencies in low bandwidth PLLs
Patent number: 9667300Abstract: A frequency synthesizer that includes a reference frequency scaler and a phase locked loop (PLL) coupled to the reference frequency scaler. The reference frequency scaler is configured to generate a first reference frequency and a second reference frequency. The PLL is configured to generate a first output frequency based on the first reference frequency during a first timeslot and a second output frequency based on the second reference frequency during a second timeslot. The PLL comprises a loop filter that includes a first switch connected in series to a first capacitor and configured to close during the first timeslot and a second switch connected in series to a second capacitor and configured to open during the first timeslot.Type: GrantFiled: June 29, 2015Date of Patent: May 30, 2017Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Jagdish Chand Goyal, Krishnaswamy Thiagarajan, Jayawardan Janardhanan, Srikanth Manian