Abstract: A fractional-N frequency synthesizer that suppresses integer boundary spurs. A frequency synthesizer includes a fractional-N phase locked loop (PLL) and a reference frequency scaler. The reference frequency scaler is coupled to a reference clock input of the PLL, the reference frequency scaler includes a programmable frequency divider, and a programmable frequency multiplier connected in series with the programmable frequency divider. Each of the divider and multiplier is configured to scale a reference frequency provided to the PLL by a programmable integer value.

Abstract: A frequency synthesizer that includes a reference frequency scaler and a phase locked loop (PLL) coupled to the reference frequency scaler. The reference frequency scaler is configured to generate a first reference frequency and a second reference frequency. The PLL is configured to generate a first output frequency based on the first reference frequency during a first timeslot and a second output frequency based on the second reference frequency during a second timeslot. The PLL comprises a loop filter that includes a first switch connected in series to a first capacitor and configured to close during the first timeslot and a second switch connected in series to a second capacitor and configured to open during the first timeslot.

Abstract: A fractional-N frequency synthesizer that suppresses integer boundary spurs. A frequency synthesizer includes a fractional-N phase locked loop (PLL) and a reference frequency scaler. The reference frequency scaler is coupled to a reference clock input of the PLL, the reference frequency scaler includes a programmable frequency divider, and a programmable frequency multiplier connected in series with the programmable frequency divider. Each of the divider and multiplier is configured to scale a reference frequency provided to the PLL by a programmable integer value.

Abstract: A method of charging a power harvested supply in an electronic communication device, which can be an NFC (near field communication) device. The power harvested supply in the electronic communication device is charged without causing dV/V violation and avoids false wake up. An RF (radio frequency) field is received at the antenna of the electronic communication device. A differential voltage is generated from the RF field at a first tag pin and a second tag pin of the electronic communication device. A bandgap reference voltage and a reference current are generated in response to the differential voltage. A shunt current is generated in response to the differential voltage and the bandgap reference voltage. A bank of switching devices is activated if the shunt current is more than the reference current.