Patents by Inventor Srikanth Ranganathan

Srikanth Ranganathan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11973231
    Abstract: A membrane electrode assembly (MEA) includes an ionically-conductive proton exchange membrane. Further, the MEA includes an anode contacting a first side of the membrane. The anode includes an anode gas diffusion layer (GDL). Further, the anode includes a first anode catalyst layer containing first catalyst particles, a hydrophobic polymer bonding agent, and a first ionomer bonding agent that lacks functional chains on a molecular backbone. The anode also includes a second anode catalyst layer containing second catalyst particles and a second ionomer bonding agent that includes functional chains on a molecular backbone. The MEA also includes a cathode contacting a second side of the membrane and comprising third catalyst particles and a cathode GDL.
    Type: Grant
    Filed: July 6, 2023
    Date of Patent: April 30, 2024
    Assignee: BLOOM ENERGY CORPORATION
    Inventors: Srikanth Ranganathan, Vijay Radhakrishnan, Vaibhav Nirgude
  • Publication number: 20230361316
    Abstract: A membrane electrode assembly (MEA) includes an ionically-conductive proton exchange membrane. Further, the MEA includes an anode contacting a first side of the membrane. The anode includes an anode gas diffusion layer (GDL). Further, the anode includes a first anode catalyst layer containing first catalyst particles, a hydrophobic polymer bonding agent, and a first ionomer bonding agent that lacks functional chains on a molecular backbone. The anode also includes a second anode catalyst layer containing second catalyst particles and a second ionomer bonding agent that includes functional chains on a molecular backbone. The MEA also includes a cathode contacting a second side of the membrane and comprising third catalyst particles and a cathode GDL.
    Type: Application
    Filed: July 6, 2023
    Publication date: November 9, 2023
    Inventors: Srikanth RANGANATHAN, Vijay RADHAKRISHNAN, Vaibhav NIRGUDE
  • Publication number: 20230231172
    Abstract: A fuel cell system includes a fuel cell stack, a fuel inlet conduit configured to provide a fuel to a fuel inlet of the fuel cell stack, an electrochemical pump separator containing an electrolyte, a cathode, and a carbon monoxide tolerant anode, a fuel exhaust conduit that operatively connects a fuel exhaust outlet of the fuel cell stack to an anode inlet of the electrochemical pump separator, and a product conduit which operatively connects a cathode outlet of the electrochemical pump separator to the fuel inlet conduit.
    Type: Application
    Filed: March 27, 2023
    Publication date: July 20, 2023
    Inventors: Chockkalingam KARUPPAIAH, Michael GASDA, Arne BALLANTINE, Martin PERRY, Andy TA, Kyle KEKELIS, Srikanth RANGANATHAN
  • Publication number: 20230155151
    Abstract: A fuel cell system and method, the system including a hotbox, a fuel cell stack disposed in the hotbox, an anode tail gas oxidizer (ATO) disposed in the hotbox, and a fuel exhaust processor fluidly connected to the hotbox. The fuel exhaust processor includes a first hydrogen pump configured to extract hydrogen from the anode exhaust received from the fuel cell stack and to output the hydrogen to a first hydrogen stream provided to the fuel cell stack, a second hydrogen pump configured to extract hydrogen from anode exhaust output from the first hydrogen pump and to output the hydrogen to the first hydrogen stream, and a third hydrogen pump configured to extract hydrogen from anode exhaust output from the second hydrogen pump and to output the hydrogen to a second hydrogen stream provided to the ATO.
    Type: Application
    Filed: November 11, 2022
    Publication date: May 18, 2023
    Inventors: Srikanth RANGANATHAN, David WEINGAERTNER, Ryan JOHNSON, Jayakumar KRISHNADASS
  • Publication number: 20230142906
    Abstract: A fuel cell system anode tail gas oxidizer (ATO) includes an inner ATO wall, an outer ATO wall, and a first catalyst ring disposed in a chamber formed between the inner ATO wall and the outer ATO wall. The first catalyst ring includes an inner wall, an outer wall, and a matrix disposed between the inner wall and the outer wall and loaded with an oxidation catalyst.
    Type: Application
    Filed: March 17, 2022
    Publication date: May 11, 2023
    Inventors: Michael PETRUCHA, John FISHER, Nilanjana BASU, Martin PERRY, Srikanth RANGANATHAN, Victor SILVA
  • Patent number: 11616249
    Abstract: A fuel cell system includes a fuel cell stack, a fuel inlet conduit configured to provide a fuel to a fuel inlet of the fuel cell stack, an electrochemical pump separator containing an electrolyte, a cathode, and a carbon monoxide tolerant anode, a fuel exhaust conduit that operatively connects a fuel exhaust outlet of the fuel cell stack to an anode inlet of the electrochemical pump separator, and a product conduit which operatively connects a cathode outlet of the electrochemical pump separator to the fuel inlet conduit.
    Type: Grant
    Filed: February 13, 2020
    Date of Patent: March 28, 2023
    Assignee: BLOOM ENERGY CORPORATION
    Inventors: Chockkalingam Karuppaiah, Michael Gasda, Arne Ballantine, Martin Perry, Andy Ta, Kyle Kekelis, Srikanth Ranganathan
  • Publication number: 20230055849
    Abstract: A method for operating a fuel cell system is provided. The method includes controlling a provision of fuel to the fuel cell system operating in a steady-state mode. The catalyst sensor is operated by providing a portion of the fuel and anode exhaust generated by the system to the catalyst sensor. Further, a change in an outlet temperature of the catalyst sensor is detected. Thereafter, it is determined whether a reformation catalyst of the catalyst sensor is poisoned by contaminants in the fuel based on the detected change in the outlet temperature.
    Type: Application
    Filed: August 22, 2022
    Publication date: February 23, 2023
    Inventors: Laxmikant GIRWALKAR, Aniket PRATAP, David WEINGAERTNER, Srikanth RANGANATHAN
  • Publication number: 20230011860
    Abstract: A fuel cell system includes a fuel cell stack configured to generate electricity, an anode exhaust and a cathode exhaust, an anode tail gas oxidizer (ATO) configured to oxidize the anode exhaust using the cathode exhaust, and a low-temperature oxidizer (LTO) configured to catalyze oxidation of carbon monoxide (CO) in the cathode exhaust output from the ATO.
    Type: Application
    Filed: July 11, 2022
    Publication date: January 12, 2023
    Inventors: Srikanth RANGANATHAN, Victor SILVA
  • Publication number: 20220367883
    Abstract: A membrane electrode assembly (MEA) includes an ionically-conductive proton exchange membrane, an anode contacting a first side of the membrane and a cathode contacting a second side of the membrane and including third catalyst particles and a cathode GDL. The anode includes an anode gas diffusion layer (GDL), a first anode catalyst layer containing first catalyst particles, a hydrophobic polymer bonding agent, and a first ionomer bonding agent that lacks functional chains on a molecular backbone, and a second anode catalyst layer containing second catalyst particles and a second ionomer bonding agent that includes functional chains on a molecular backbone.
    Type: Application
    Filed: May 15, 2022
    Publication date: November 17, 2022
    Inventors: Srikanth RANGANATHAN, Vijay RADHAKRISHNAN, Vaibhav NIRGUDE
  • Publication number: 20220328856
    Abstract: A carbon monoxide (CO) tolerant membrane electrode assembly (MEA) includes an ionically-conductive proton exchange membrane, an anode contacting a first side of the membrane and including a hydrophobic bonding agent, an ionomer bonding agent, first catalyst particles, second catalyst particles, and an anode gas diffusion layer (GDL), a cathode contacting a second side of the membrane and including a cathode GDL. The first catalyst particles are configured to preferentially catalyze oxidation of CO, and the second catalyst particles are configured to preferentially catalyze generation of hydrogen ions.
    Type: Application
    Filed: April 7, 2022
    Publication date: October 13, 2022
    Inventors: Vijay RADHAKRISHNAN, Srikanth RANGANATHAN, M.K. PREMKUMAR
  • Patent number: 10853244
    Abstract: A method of writing data to a DNA strand comprises cutting an address block of a selected address-data block unit of the DNA strand to form first and second DNA strings, and inserting a replacement address-data block that includes a replacement data segment between the first DNA string and the second DNA string to provide a rewritten DNA strand having valid address followed by valid data and an invalid address followed by invalid data.
    Type: Grant
    Filed: May 25, 2017
    Date of Patent: December 1, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Christopher Petti, Srikanth Ranganathan
  • Patent number: 10797061
    Abstract: Three-dimensional memory devices include structures that induce a vertical tensile stress in vertical semiconductor channels to enhance charge carrier mobility. Vertical tensile stress may be induced by a laterally compressive stress applied by stressor pillar structure. The stressor pillar structures can include a stressor material such as a dielectric metal oxide material, silicon nitride, thermal silicon oxide or a semiconductor material having a greater lattice constant than that of the channel. Vertical tensile stress may be induced by a compressive stress applied by electrically conductive layers that laterally surround the vertical semiconductor channel, or by a stress memorization technique that captures a compressive stress from sacrificial material layers. Vertical tensile stress can be generated by a source-level pinning layer that prevents vertical expansion of the vertical semiconductor channel.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: October 6, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Akio Nishida, Toshihiro Iizuka, Rahul Sharangpani, Raghuveer S. Makala, Adarsh Rajashekhar, Fei Zhou, Srikanth Ranganathan
  • Patent number: 10797060
    Abstract: Three-dimensional memory devices include structures that induce a vertical tensile stress in vertical semiconductor channels to enhance charge carrier mobility. Vertical tensile stress may be induced by a laterally compressive stress applied by stressor pillar structure. The stressor pillar structures can include a stressor material such as a dielectric metal oxide material, silicon nitride, thermal silicon oxide or a semiconductor material having a greater lattice constant than that of the channel. Vertical tensile stress may be induced by a compressive stress applied by electrically conductive layers that laterally surround the vertical semiconductor channel, or by a stress memorization technique that captures a compressive stress from sacrificial material layers. Vertical tensile stress can be generated by a source-level pinning layer that prevents vertical expansion of the vertical semiconductor channel.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: October 6, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Rahul Sharangpani, Raghuveer S. Makala, Adarsh Rajashekhar, Fei Zhou, Srikanth Ranganathan, Akio Nishida, Toshihiro Iizuka
  • Publication number: 20200303758
    Abstract: A fuel cell system includes a fuel cell stack, a fuel inlet conduit configured to provide a fuel to a fuel inlet of the fuel cell stack, an electrochemical pump separator containing an electrolyte, a cathode, and a carbon monoxide tolerant anode, a fuel exhaust conduit that operatively connects a fuel exhaust outlet of the fuel cell stack to an anode inlet of the electrochemical pump separator, and a product conduit which operatively connects a cathode outlet of the electrochemical pump separator to the fuel inlet conduit.
    Type: Application
    Filed: February 13, 2020
    Publication date: September 24, 2020
    Inventors: Chockkalingam KARUPPAIAH, Michael GASDA, Arne BALLANTINE, Martin PERRY, Andy TA, Kyle KEKELIS, Srikanth RANGANATHAN
  • Publication number: 20200194445
    Abstract: Three-dimensional memory devices include structures that induce a vertical tensile stress in vertical semiconductor channels to enhance charge carrier mobility. Vertical tensile stress may be induced by a laterally compressive stress applied by stressor pillar structure. The stressor pillar structures can include a stressor material such as a dielectric metal oxide material, silicon nitride, thermal silicon oxide or a semiconductor material having a greater lattice constant than that of the channel. Vertical tensile stress may be induced by a compressive stress applied by electrically conductive layers that laterally surround the vertical semiconductor channel, or by a stress memorization technique that captures a compressive stress from sacrificial material layers. Vertical tensile stress can be generated by a source-level pinning layer that prevents vertical expansion of the vertical semiconductor channel.
    Type: Application
    Filed: December 17, 2018
    Publication date: June 18, 2020
    Inventors: Rahul SHARANGPANI, Raghuveer S. MAKALA, Adarsh RAJASHEKHAR, Fei ZHOU, Srikanth RANGANATHAN, Akio NISHIDA, Toshikazu IIZUKA
  • Publication number: 20200194446
    Abstract: Three-dimensional memory devices include structures that induce a vertical tensile stress in vertical semiconductor channels to enhance charge carrier mobility. Vertical tensile stress may be induced by a laterally compressive stress applied by stressor pillar structure. The stressor pillar structures can include a stressor material such as a dielectric metal oxide material, silicon nitride, thermal silicon oxide or a semiconductor material having a greater lattice constant than that of the channel. Vertical tensile stress may be induced by a compressive stress applied by electrically conductive layers that laterally surround the vertical semiconductor channel, or by a stress memorization technique that captures a compressive stress from sacrificial material layers. Vertical tensile stress can be generated by a source-level pinning layer that prevents vertical expansion of the vertical semiconductor channel.
    Type: Application
    Filed: December 17, 2018
    Publication date: June 18, 2020
    Inventors: Akio NISHIDA, Toshikazu IIZUKA, Rahul SHARANGPANI, Raghuveer S. MAKALA, Adarsh RAJASHEKHAR, Fei ZHOU, Srikanth RANGANATHAN
  • Patent number: 10109680
    Abstract: A method is provided that includes forming a word line above a substrate, forming a bit line above the substrate, forming a nonvolatile memory material between the word line and the bit line, the nonvolatile memory material including a semiconductor material layer and a conductive oxide material layer, forming a barrier material layer between the semiconductor material layer and the conductive oxide material layer, and forming a memory cell including the nonvolatile memory material at an intersection of the bit line and the word line. The word line is disposed in a first direction, the bit line is disposed in a second direction perpendicular to the first direction. The barrier material layer has an ionic conductivity of greater than about 0.1 Siemens/cm @ 1000° C.
    Type: Grant
    Filed: June 14, 2017
    Date of Patent: October 23, 2018
    Assignee: SanDisk Technologies LLC
    Inventors: Sebastian J. M. Wicklein, Juan P. Saenz, Srikanth Ranganathan, Ming-Che Wu, Tanmay Kumar
  • Publication number: 20180157587
    Abstract: A method of writing data to a DNA strand comprises cutting an address block of a selected address-data block unit of the DNA strand to form first and second DNA strings, and inserting a replacement address-data block that includes a replacement data segment between the first DNA string and the second DNA string to provide a rewritten DNA strand having valid address followed by valid data and an invalid address followed by invalid data.
    Type: Application
    Filed: May 25, 2017
    Publication date: June 7, 2018
    Inventors: Christopher PETTI, Srikanth RANGANATHAN
  • Patent number: 9842857
    Abstract: A method of manufacturing a semiconductor structure includes forming a stack of alternating layers comprising insulating layers and spacer material layers over a semiconductor substrate, forming a memory opening through the stack, forming an aluminum oxide layer having a horizontal portion at a bottom of the memory opening and a vertical portion at least over a sidewall of the memory opening, where the horizontal portion differs from the vertical portion by at least one of structure or composition, and selectively etching the horizontal portion selective to the vertical portion.
    Type: Grant
    Filed: February 23, 2017
    Date of Patent: December 12, 2017
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Rahul Sharangpani, Sateesh Koka, Raghuveer S. Makala, Srikanth Ranganathan, Mark Juanitas, Johann Alsmeier
  • Publication number: 20170162597
    Abstract: A method of manufacturing a semiconductor structure includes forming a stack of alternating layers comprising insulating layers and spacer material layers over a semiconductor substrate, forming a memory opening through the stack, forming an aluminum oxide layer having a horizontal portion at a bottom of the memory opening and a vertical portion at least over a sidewall of the memory opening, where the horizontal portion differs from the vertical portion by at least one of structure or composition, and selectively etching the horizontal portion selective to the vertical portion.
    Type: Application
    Filed: February 23, 2017
    Publication date: June 8, 2017
    Inventors: Rahul Sharangpani, Sateesh Koka, Raghuveer S. Makala, Srikanth Ranganathan, Mark Juanitas, Johann Alsmeier