Abstract: An architecture for content-aware compression and/or encryption of various segments of a application is disclosed. The architecture advantageously allows decompression and decryption units to be placed various levels of a memory hierarchy.

Abstract: A computer implemented technique framework, prototype tool and associated methods that provide a high degree of visibility and control over the in-field execution of software in a minimally intrusive manner wherein developer-defined correctness tests and validation logic are embedded into the sensor node itself, making in-field software testing autonomous without necessitating continuous developer participation.

Abstract: A method of storing addresses in a database comprising generating original prefixes representing the addresses to be stored in the database. The prefix lengths are determined dynamically. Reduced prefixes are generated by collapsing or expanding the original prefixes such that a number of reduced prefixes is less than a number of original prefixes. The reduced prefixes are stored in the database.

Abstract: A voice based multimodal speaker authentication method and telecommunications application thereof employing a speaker adaptive method for training phenome specific Gaussian mixture models. Applied to telecommunications services, the method may advantageously be implemented in contemporary wireless terminals.

Abstract: An embedded systems architecture is disclosed which can flexibly handle compression of both instruction code and data.

Abstract: An integrated circuit comprising at least one system level decompressor and at least a first hardware block associated with a core level decompressor. The system level decompressor is capable of performing system level decompression of received compressed test data to form partially decompressed test data. The core level decompressor being capable of performing core level decompression of the partially decompressed test data.

Abstract: A method and system usable in sensor networks for handling memory faults is disclosed. In order to protect the operating system of a sensor node, coarse-grained memory protection is provided by creating and enforcing an application fault domain in the data memory address space of the sensor node. The data memory accessed by the application modules is restricted to the region (which defines the application fault domain) within the data memory address space. The application modules are prevented from accessing memory outside the application fault domain through software-based run-time checks. The state belonging to the operations system is maintained outside of the application fault domain, and is thus protected from memory corruption from any application module. In order to ensure that an application module does not operate on a corrupted state, fine-grained error detection and recovery is provided within the application fault domain.

Abstract: An architecture and method for data storage and retrieval which also addresses a number of key problems associated with systems employing hash-based techniques. The architecture and method employs a collision-free hashing scheme called Bloomier filter while eliminates its false positives in a storage efficient way. Wildcard support is added through the use of a scheme called prefix collapsing, while introducing only a small additional storage requirement and reduced hardware complexity. Real update traces indicate that both fast and incremental updates are provided—features generally not available in prior-art collision-free hashing schemes.

Abstract: Determining a test point location in a structured application specific integrated circuit (ASIC) includes using one or more unused cells of the structured ASIC. In particular, an unused cell of the structured ASIC is identified and then a test point is inserted at the unused cell of the structured ASIC (e.g., if the unused cell is neighboring at least one used cell of the structured ASIC).

Abstract: Disclosed is a logic testing system that includes a decompressor and a tester in communication with the decompressor. The tester is configured to store a seed and locations of scan inputs and is further configured to transmit the seed and the locations of scan inputs to the decompressor. The decompressor is configured to generate a test pattern from the seed and the locations of scan inputs. The decompressor includes a first test pattern generator, a second test pattern generator, and a selector configured to select the test pattern generated by the first test pattern generator or the test pattern generated by the second test pattern generator using the locations of scan inputs.

Abstract: A security policy associated with a system is evaluated. The system includes a communication bus having a data bus and a plurality of components interconnected via the communication bus. The system also includes a circuit configured to evaluate a security policy associated with the system by reading at least one data bus signal associated with a transaction between at least two of the plurality of components.

Abstract: A spatial compactor design and technique for the compaction of test response data is herein disclosed which advantageously provides a scan-out response with multiple opportunities to be observed on different output channels in one to several scan-shift cycles.

Abstract: A method for code compression of a program, the method comprising separating code from data. Software transformations necessary to make address mappings between compressed and uncompressed space are introduced into the code. Statistics are obtained about frequency of occurrence instructions, wherein said statistics include frequency of occurrence of two consecutive instructions. The program is parsed to identify occurrence of instructions or instruction pairs. The identified instructions are replaced with an address to a compressed bus-word table. An address mapping is generated from uncompressed address to compressed addresses.

Abstract: A storage management architecture is disclosed which is particularly advantageous for devices such as embedded systems. The architecture provides a framework for a compression/decompression system which advantageously is software-based and which facilitates the compression of both instruction code and writeable data.

Abstract: A dynamic memory compression architecture is disclosed which allows applications with working data sets exceeding the physical memory of an embedded system to still execute correctly. The dynamic memory compression architecture provides “on-the-fly” compression and decompression of the working data in a manner which is transparent to the user and which does not require special-purpose hardware. A new compression technique is also herein disclosed which is particularly advantageous when utilized with the above-mentioned dynamic memory compression architecture.

Abstract: A logic circuit comprising at least one input, one output and a delay fault circuit. The delay fault circuit includes a first standard scan cell, a combinational test point positioned immediately after the first standard scan cell in a scan chain and a second standard scan cell positioned immediately after the combinational test point in the scan chain.

Abstract: A test output compaction arrangement and a method of generating control patterns for unknown blocking is herein disclosed. The specified bits in the control patterns, which when using linear feedback shift register (LFSR) reseeding determines control data volume and LFSR size, are preferably organized in a manner so as to balance the number of specified bits in the control patterns across test patterns.

Abstract: The invention is an efficient system and method for re-partitioning an existing system-level design by boosting the fraction of system functionality that is implemented using embedded software. The invention comprises automated techniques for identifying hardware targets to be softened and techniques for automatically generating a new system-level architecture having a new hardware/software boundary.

Abstract: An information retrieval architecture is herein disclosed which can handle multi-dimensional search problems such as packet classification.

Abstract: A method of storing addresses in a database comprising generating original prefixes representing the addresses to be stored in the database. The prefix lengths are determined dynamically. Reduced prefixes are generated by collapsing or expanding the original prefixes such that a number of reduced prefixes is less than a number of original prefixes. The reduced prefixes are stored in the database.