Abstract: A network router comprising at least one index table operable to store encoded values of a function associated with an input source address in at least two locations. The encoded values are obtained by hashing the input source address such that all the encoded values must be used to recover the function. At least one filtering table is provided that is operable to store prefixes of at least two different lengths, the prefixes corresponding to network addresses. The filtering table is indexed by entries in said index table. At least one result table is provided. The result table is operable to be indexed by entries in said index table. The result table stores destination addresses. At least one record in the filtering table has a prefix length field that is operable to store a prefix length of a prefix stored in said at least one record.

Abstract: The present invention is directed to a logic testing architecture with an improved decompression engine that compresses the seeds of a linear test pattern generator in a manner that is independent of the test pattern set.

Abstract: An embedded systems architecture is disclosed which can flexibly handle compression of both instruction code and data.

Abstract: An improved test output compaction architecture and method is disclosed that takes advantage of a response shaper in order to minimize masking of faults during compaction.

Abstract: A power estimation framework based on a network of power monitors that observe component- and system-level execution and power statistics at run time. Based on those statistics, the power monitors (i) select between multiple alternative power models for each component and/or (ii) configure the component power models to best negotiate the trade-off between efficiency and accuracy. This approach effectuates a co-coordinated, adaptive, spatio-temporal allocation of computational effort for power estimation. This approach yields large reductions in power estimation overhead while minimally impacting power estimation accuracy.

Abstract: A new compression and decompression architecture is herein disclosed which advantageously uses a plurality of parallel content addressable memories of different sizes to perform fast matching during compression.

Abstract: The present invention is directed to a logic testing architecture with an improved decompression engine and a method of decompressing scan chains for testing logic circuits.

Abstract: An architecture for content-aware compression and/or encryption of various segments of a application is disclosed. The architecture advantageously allows decompression and decryption units to be placed various levels of a memory hierarchy.

Abstract: A system architecture is disclosed that can support fast random access to encrypted memory.

Abstract: The present invention is directed to improved delay fault testing by optimizing the order of scan cells in a scan chain.

Abstract: A system comprising at least one host processor, at least one security processor and a first memory that is exclusively accessible only by the security processor.

Abstract: A content-based information retrieval architecture is herein disclosed that can achieve correct and predictable high speed lookups while taking advantage of inexpensive conventional memory components.

Abstract: An integrated circuit comprising at least one system level decompressor and at least a first hardware block associated with a core level decompressor. The system level decompressor is capable of performing system level decompression of received compressed test data to form partially decompressed test data. The core level decompressor being capable of performing core level decompression of the partially decompressed test data.

Abstract: A scan-based method for testing delay faults in a circuit comprising controlling a subset of state inputs of the circuit by a skewed-load approach and controlling all inputs other than said subset of state inputs by a broad-side approach.

Abstract: A logic circuit comprising at least one input, one output and a delay fault circuit. The delay fault circuit includes a first standard scan cell, a combinational test point positioned immediately after the first standard scan cell in a scan chain and a second standard scan cell positioned immediately after the combinational test point in the scan chain.

Abstract: A method for code compression of a program, the method comprising separating code from data. Software transformations necessary to make address mappings between compressed and uncompressed space are introduced into the code. Statistics are obtained about frequency of occurrence instructions, wherein said statistics include frequency of occurrence of two consecutive instructions. The program is parsed to identify occurrence of instructions or instruction pairs. The identified instructions are replaced with an address to a compressed bus-word table. An address mapping is generated from uncompressed address to compressed addresses.

Abstract: A method, system and a computer product for a new partial scan technique that incurs significantly less overhead than the full-scan technique and yet achieves very high test coverage in short CPU times are provided. Scan memory elements are selected so that the scanned circuit satisfies two key properties in the test mode. First, the scanned circuit has partitions that are peripherally interacting finite state machines (peripheral partitions). Second, the memory element dependency graph (S-graph) of each peripheral partition of the scanned circuit has a tree structure. An efficient for algorithm peripheral partitioning and tree decomposition is provided. The scan memory element selection algorithm iteratively partitions the S-graph into disjoint sub-graphs with the tree structure.

Abstract: A programmable security processor for efficient execution of security protocols, wherein the instruction set of the processor is enhanced to contain at least one instruction that is used to improve the efficiency of a public-key cryptographic algorithm, and at least one instruction that is used to improve the efficiency of a private-key cryptographic algorithm.

Abstract: A method, system and a computer product for a new partial scan technique that incurs significantly less overhead than the full-scan technique and yet achieves very high test coverage in short CPU times are provided. Scan memory elements are selected so that the scanned circuit satisfies two key properties in the test mode. First, the scanned circuit has partitions that are peripherally interacting finite state machines (peripheral partitions). Second, the memory element dependency graph (S-graph) of each peripheral partition of the scanned circuit has a tree structure. An efficient for algorithm peripheral partitioning and tree decomposition is provided. The scan memory element selection algorithm iteratively partitions the S-graph into disjoint sub-graphs with the tree structure.

Abstract: A method for fast static compaction in sequential circuits with finite output states by removing subsequences of test vectors from a vector test set. The method has the following steps: (1) relaxing the output states of the sequential circuits; (2) identifying a candidate subsequence of test vectors from the vector test set for removal; (3) temporarily removing the candidate subsequence of test vectors from the vector test set; (4) performing fault simulation on remaining test vectors from the vector test set; (5) examining fault simulation results against a set of removal criteria; (6) permanently removing the temporarily removed candidate subsequence if said set of removal criteria are met; (7) replacing the temporarily removed candidate subsequence if said set of removal criteria are not met; and (8) repeating steps (1) through (7) until all candidate subsequences of test vectors have been identified.