Abstract: Embodiments of the present invention disclose a method, computer program product, and system for determining statistics corresponding to data transfer operations. In one embodiment, the computer implemented method includes the steps of receiving a request from an input/output (I/O) device to perform a data transfer operation between the I/O device and a memory, generating an entry in an input/output memory management unit (IOMMU) corresponding to the data transfer operation, wherein the entry in the IOMMU includes at least an indication of a processor chip that corresponds to the memory of the data transfer operation, monitoring the data transfer operation between the I/O device and the memory, determining statistics corresponding to the monitored data transfer operation, wherein the determined statistics include at least: the I/O device that performed the data transfer operation, the processor chip that corresponds to the memory of the data transfer operation, and an amount of data transferred.

Abstract: A system can translate an input/output (I/O) direct memory access (DMA) address to a physical system memory address in a data processing system. In response to receiving a DMA packet containing a requester identity (RID) associated with a partitionable endpoint (PE) number and an I/O DMA address, the system can retrieve an entry associated with the RID from a first translation validation table (TVT). Using that entry, the system can validate the number of TVT entries and extract from the I/O DMA address an offset. This offset can be validated and used to retrieve an entry in a second TVT. Data from this entry can be validated and the system can use this to access another table to retrieve the translation to the physical system memory address.

Abstract: A method, system and computer program product are provided for implementing coherent accelerator function isolation for virtualization in an input/output (IO) adapter in a computer system. A coherent accelerator provides accelerator function units (AFUs), each AFU is adapted to operate independently of the other AFUs to perform a computing task that can be implemented within application software on a processor. The AFU has access to system memory bound to the application software and is adapted to make copies of that memory within AFU memory-cache in the AFU. As part of this memory coherency domain, each of the AFU memory-cache and processor memory-cache is adapted to be aware of changes to data commonly in either cache as well as data changed in memory of which the respective cache contains a copy.

Abstract: A method, system and computer program product are provided for implementing coherent accelerator function isolation for virtualization in an input/output (IO) adapter in a computer system. A coherent accelerator provides accelerator function units (AFUs), each AFU is adapted to operate independently of the other AFUs to perform a computing task that can be implemented within application software on a processor. The AFU has access to system memory bound to the application software and is adapted to make copies of that memory within AFU memory-cache in the AFU. As part of this memory coherency domain, each of the AFU memory-cache and processor memory-cache is adapted to be aware of changes to data commonly in either cache as well as data changed in memory of which the respective cache contains a copy.

Abstract: Tracking data transfers in an input/output adapter card system to determine whether the adapter cards are well-placed with respect to the components (for example dynamic random access memories) with which the adapter cards respectively are observed to communicate data. Some embodiments use a heuristic value for each adapter card in the system based on inter node transfers and intra node transfers, which are separately weighted and summed over some predetermined time interval in order to obtain the heuristic value.

Abstract: Tracking data transfers in an input/output adapter card system to determine whether the adapter cards are well-placed with respect to the components (for example dynamic random access memories) with which the adapter cards respectively are observed to communicate data. Some embodiments use a heuristic value for each adapter card in the system based on inter node transfers and intra node transfers, which are separately weighted and summed over some predetermined time interval in order to obtain the heuristic value.

Abstract: A method, system and computer program product are provided for implementing coherent accelerator function isolation for virtualization in an input/output (IO) adapter in a computer system. A coherent accelerator provides accelerator function units (AFUs), each AFU is adapted to operate independently of the other AFUs to perform a computing task that can be implemented within application software on a processor. The AFU has access to system memory bound to the application software and is adapted to make copies of that memory within AFU memory-cache in the AFU. As part of this memory coherency domain, each of the AFU memory-cache and processor memory-cache is adapted to be aware of changes to data commonly in either cache as well as data changed in memory of which the respective cache contains a copy.

Abstract: A method, system and computer program product are provided for implementing coherent accelerator function isolation for virtualization in an input/output (IO) adapter in a computer system. A coherent accelerator provides accelerator function units (AFUs), each AFU is adapted to operate independently of the other AFUs to perform a computing task that can be implemented within application software on a processor. The AFU has access to system memory bound to the application software and is adapted to make copies of that memory within AFU memory-cache in the AFU. As part of this memory coherency domain, each of the AFU memory-cache and processor memory-cache is adapted to be aware of changes to data commonly in either cache as well as data changed in memory of which the respective cache contains a copy.

Abstract: A method, system and computer program product are provided for implementing coherent accelerator function isolation for virtualization in an input/output (IO) adapter in a computer system. A coherent accelerator provides accelerator function units (AFUs), each AFU is adapted to operate independently of the other AFUs to perform a computing task that can be implemented within application software on a processor. The AFU has access to system memory bound to the application software and is adapted to make copies of that memory within AFU memory-cache in the AFU. As part of this memory coherency domain, each of the AFU memory-cache and processor memory-cache is adapted to be aware of changes to data commonly in either cache as well as data changed in memory of which the respective cache contains a copy.

Abstract: Embodiments of the present invention disclose a method, computer program product, and system for determining statistics corresponding to data transfer operations. In one embodiment, the computer implemented method includes the steps of receiving a request from an input/output (I/O) device to perform a data transfer operation between the I/O device and a memory, generating an entry in an input/output memory management unit (IOMMU) corresponding to the data transfer operation, wherein the entry in the IOMMU includes at least an indication of a processor chip that corresponds to the memory of the data transfer operation, monitoring the data transfer operation between the I/O device and the memory, determining statistics corresponding to the monitored data transfer operation, wherein the determined statistics include at least: the I/O device that performed the data transfer operation, the processor chip that corresponds to the memory of the data transfer operation, and an amount of data transferred.

Abstract: Embodiments of the present invention disclose a method, computer program product, and system for determining statistics corresponding to data transfer operations. In one embodiment, the computer implemented method includes the steps of receiving a request from an input/output (I/O) device to perform a data transfer operation between the I/O device and a memory, generating an entry in an input/output memory management unit (IOMMU) corresponding to the data transfer operation, wherein the entry in the IOMMU includes at least an indication of a processor chip that corresponds to the memory of the data transfer operation, monitoring the data transfer operation between the I/O device and the memory, determining statistics corresponding to the monitored data transfer operation, wherein the determined statistics include at least: the I/O device that performed the data transfer operation, the processor chip that corresponds to the memory of the data transfer operation, and an amount of data transferred.

Abstract: Embodiments of the present invention disclose a method, computer program product, and system for determining statistics corresponding to data transfer operations. In one embodiment, the computer implemented method includes the steps of receiving a request from an input/output (I/O) device to perform a data transfer operation between the I/O device and a memory, generating an entry in an input/output memory management unit (IOMMU) corresponding to the data transfer operation, wherein the entry in the IOMMU includes at least an indication of a processor chip that corresponds to the memory of the data transfer operation, monitoring the data transfer operation between the I/O device and the memory, determining statistics corresponding to the monitored data transfer operation, wherein the determined statistics include at least: the I/O device that performed the data transfer operation, the processor chip that corresponds to the memory of the data transfer operation, and an amount of data transferred.

Abstract: A system can translate an input/output (I/O) direct memory access (DMA) address to a physical system memory address in a data processing system. In response to receiving a DMA packet containing a requester identity (RID) associated with a partitionable endpoint (PE) number and an I/O DMA address, the system can retrieve an entry associated with the RID from a first translation validation table (TVT). Using that entry, the system can validate the number of TVT entries and extract from the I/O DMA address an offset. This offset can be validated and used to retrieve an entry in a second TVT. Data from this entry can be validated and the system can use this to access another table to retrieve the translation to the physical system memory address.

Abstract: A method, system and computer program product are provided for implementing coherent accelerator function isolation for virtualization in an input/output (IO) adapter in a computer system. A coherent accelerator provides accelerator function units (AFUs), each AFU is adapted to operate independently of the other AFUs to perform a computing task that can be implemented within application software on a processor. The AFU has access to system memory bound to the application software and is adapted to make copies of that memory within AFU memory-cache in the AFU. As part of this memory coherency domain, each of the AFU memory-cache and processor memory-cache is adapted to be aware of changes to data commonly in either cache as well as data changed in memory of which the respective cache contains a copy.

Abstract: Tracking data transfers in an input/output adapter card system to determine whether the adapter cards are well-placed with respect to the components (for example dynamic random access memories) with which the adapter cards respectively are observed to communicate data. Some embodiments use a heuristic value for each adapter card in the system based on inter node transfers and intra node transfers, which are separately weighted and summed over some predetermined time interval in order to obtain the heuristic value.

Abstract: Tracking data transfers in an input/output adapter card system to determine whether the adapter cards are well-placed with respect to the components (for example dynamic random access memories) with which the adapter cards respectively are observed to communicate data. Some embodiments use a heuristic value for each adapter card in the system based on inter node transfers and intra node transfers, which are separately weighted and summed over some predetermined time interval in order to obtain the heuristic value.

Abstract: Tracking data transfers in an input/output adapter card system to determine whether the adapter cards are well-placed with respect to the components (for example dynamic random access memories) with which the adapter cards respectively are observed to communicate data. Some embodiments use a heuristic value for each adapter card in the system based on inter node transfers and intra node transfers, which are separately weighted and summed over some predetermined time interval in order to obtain the heuristic value.

Abstract: DMA translation table entries include a consecutive count (CC) field that indicates how many subsequent translation table entries point to successive real page numbers. A DMA address translation mechanism stores a value in the CC field when a translation table entry is stored, and updates the CC field in other affected translation table entries as well. When a translation table entry is read, and the CC field is non-zero, the DMA controller can use multiple RPNs from the access to the single translation table entry. Thus, if a translation table entry has a value of 2 in the CC field, the DMA address translation mechanism knows it can access the real page number (RPN) corresponding to the translation table entry, and also knows it can access the two subsequent RPNs without the need of reading the next two subsequent translation table entries.

Abstract: DMA translation table entries include a consecutive count (CC) field that indicates how many subsequent translation table entries point to successive real page numbers. A DMA address translation mechanism stores a value in the CC field when a translation table entry is stored, and updates the CC field in other affected translation table entries as well. When a translation table entry is read, and the CC field is non-zero, the DMA controller can use multiple RPNs from the access to the single translation table entry. Thus, if a translation table entry has a value of 2 in the CC field, the DMA address translation mechanism knows it can access the real page number (RPN) corresponding to the translation table entry, and also knows it can access the two subsequent RPNs without the need of reading the next two subsequent translation table entries.

Abstract: Tracking data transfers in an input/output adapter card system to determine whether the adapter cards are well-placed with respect to the components (for example dynamic random access memories) with which the adapter cards respectively are observed to communicate data. Some embodiments use a heuristic value for each adapter card in the system based on inter node transfers and intra node transfers, which are separately weighted and summed over some predetermined time interval in order to obtain the heuristic value.