Patents by Inventor Srinivas KOTTA
Srinivas KOTTA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20150317274Abstract: A method, system and computer program product are provided for implementing coherent accelerator function isolation for virtualization in an input/output (IO) adapter in a computer system. A coherent accelerator provides accelerator function units (AFUs), each AFU is adapted to operate independently of the other AFUs to perform a computing task that can be implemented within application software on a processor. The AFU has access to system memory bound to the application software and is adapted to make copies of that memory within AFU memory-cache in the AFU. As part of this memory coherency domain, each of the AFU memory-cache and processor memory-cache is adapted to be aware of changes to data commonly in either cache as well as data changed in memory of which the respective cache contains a copy.Type: ApplicationFiled: May 5, 2014Publication date: November 5, 2015Applicant: International Business Machines CorporationInventors: Jesse P. Arroyo, Srinivas Kotta, Gregory M. Nordstrom, Timothy J. Schimke
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Publication number: 20150317275Abstract: A method, system and computer program product are provided for implementing coherent accelerator function isolation for virtualization in an input/output (IO) adapter in a computer system. A coherent accelerator provides accelerator function units (AFUs), each AFU is adapted to operate independently of the other AFUs to perform a computing task that can be implemented within application software on a processor. The AFU has access to system memory bound to the application software and is adapted to make copies of that memory within AFU memory-cache in the AFU. As part of this memory coherency domain, each of the AFU memory-cache and processor memory-cache is adapted to be aware of changes to data commonly in either cache as well as data changed in memory of which the respective cache contains a copy.Type: ApplicationFiled: February 20, 2015Publication date: November 5, 2015Inventors: Jesse P. Arroyo, Srinivas Kotta, Gregory M. Nordstrom, Timothy J. Schimke
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Publication number: 20150309948Abstract: Embodiments of the present invention disclose a method, computer program product, and system for determining statistics corresponding to data transfer operations. In one embodiment, the computer implemented method includes the steps of receiving a request from an input/output (I/O) device to perform a data transfer operation between the I/O device and a memory, generating an entry in an input/output memory management unit (IOMMU) corresponding to the data transfer operation, wherein the entry in the IOMMU includes at least an indication of a processor chip that corresponds to the memory of the data transfer operation, monitoring the data transfer operation between the I/O device and the memory, determining statistics corresponding to the monitored data transfer operation, wherein the determined statistics include at least: the I/O device that performed the data transfer operation, the processor chip that corresponds to the memory of the data transfer operation, and an amount of data transferred.Type: ApplicationFiled: June 23, 2014Publication date: October 29, 2015Inventors: Srinivas Kotta, Mehulkumar J. Patel, Venkatesh Sainath, Vaidyanathan Srinivasan
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Publication number: 20150309947Abstract: Embodiments of the present invention disclose a method, computer program product, and system for determining statistics corresponding to data transfer operations. In one embodiment, the computer implemented method includes the steps of receiving a request from an input/output (I/O) device to perform a data transfer operation between the I/O device and a memory, generating an entry in an input/output memory management unit (IOMMU) corresponding to the data transfer operation, wherein the entry in the IOMMU includes at least an indication of a processor chip that corresponds to the memory of the data transfer operation, monitoring the data transfer operation between the I/O device and the memory, determining statistics corresponding to the monitored data transfer operation, wherein the determined statistics include at least: the I/O device that performed the data transfer operation, the processor chip that corresponds to the memory of the data transfer operation, and an amount of data transferred.Type: ApplicationFiled: April 29, 2014Publication date: October 29, 2015Applicant: International Business Machines CorporationInventors: Srinivas Kotta, Mehulkumar J. Patel, Venkatesh Sainath, Vaidyanathan Srinivasan
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Patent number: 9141493Abstract: Instead of disabling PCI communication between system resources in a host computing device and I/O devices when a PCI Host Bridge (PHB) is unable to function, the host computing device may include a redundant PCI communication path for maintaining communication between the system resources and the I/O devices after a first PHB experiences an unrecoverable error. In one embodiment, the redundant PCI communication path includes a second PHB that is maintained in a standby state so long as the first PHB is functioning normally. However, once the first PHB experiences an unrecoverable error, the second PHB is changed to the master state and assumes the responsibility for maintaining communication between the system resources and the I/O devices.Type: GrantFiled: July 12, 2013Date of Patent: September 22, 2015Assignee: International Business Machines CorporationInventors: Jesse P. Arroyo, Srinivas Kotta, Anjam Kumar Guttahalli Krishna
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Patent number: 9141494Abstract: Instead of disabling PCI communication between system resources in a host computing device and I/O devices when a PCI Host Bridge (PHB) is unable to function, the host computing device may include a redundant PCI communication path for maintaining communication between the system resources and the I/O devices after a first PHB experiences an unrecoverable error. In one embodiment, the redundant PCI communication path includes a second PHB that is maintained in a standby state so long as the first PHB is functioning normally. However, once the first PHB experiences an unrecoverable error, the second PHB is changed to the master state and assumes the responsibility for maintaining communication between the system resources and the I/O devices.Type: GrantFiled: December 8, 2014Date of Patent: September 22, 2015Assignee: International Business Machines CorporationInventors: Jesse P. Arroyo, Srinivas Kotta, Anjan Kumar Guttahalli Krishna
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Patent number: 9092399Abstract: Instead of disabling PCI communication between system resources in a host computing device and I/O devices when a PCI Host Bridge (PHB) is unable to function, the host computing device may include a redundant PCI communication path for maintaining communication between the system resources and the I/O devices after a first PHB experiences an unrecoverable error. In one embodiment, the redundant PCI communication path includes a second PHB that is maintained in a standby state so long as the first PHB is functioning normally. However, once the first PHB experiences an unrecoverable error, the second PHB is changed to the master state and assumes the responsibility for maintaining communication between the system resources and the I/O devices.Type: GrantFiled: July 12, 2013Date of Patent: July 28, 2015Assignee: International Business Machines CorporationInventors: Jesse P. Arroyo, Srinivas Kotta, Anjam Kumar Guttahalli Krishna
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Publication number: 20150186171Abstract: Tracking data transfers in an input/output adapter card system to determine whether the adapter cards are well-placed with respect to the components (for example dynamic random access memories) with which the adapter cards respectively are observed to communicate data. Some embodiments use a heuristic value for each adapter card in the system based on inter node transfers and intra node transfers, which are separately weighted and summed over some predetermined time interval in order to obtain the heuristic value.Type: ApplicationFiled: December 27, 2013Publication date: July 2, 2015Applicant: International Business Machines CorporationInventors: Srinivas Kotta, Mehulkumar J. Patel, Venkatesh Sainath, Vaidyanathan Srinivasan
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Publication number: 20150186323Abstract: Tracking data transfers in an input/output adapter card system to determine whether the adapter cards are well-placed with respect to the components (for example dynamic random access memories) with which the adapter cards respectively are observed to communicate data. Some embodiments use a heuristic value for each adapter card in the system based on inter node transfers and intra node transfers, which are separately weighted and summed over some predetermined time interval in order to obtain the heuristic value.Type: ApplicationFiled: June 20, 2014Publication date: July 2, 2015Inventors: Srinivas Kotta, Mehulkumar J. Patel, Venkatesh Sainath, Vaidyanathan Srinivasan
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Publication number: 20150095700Abstract: Instead of disabling PCI communication between system resources in a host computing device and I/O devices when a PCI Host Bridge (PHB) is unable to function, the host computing device may include a redundant PCI communication path for maintaining communication between the system resources and the I/O devices after a first PHB experiences an unrecoverable error. In one embodiment, the redundant PCI communication path includes a second PHB that is maintained in a standby state so long as the first PHB is functioning normally. However, once the first PHB experiences an unrecoverable error, the second PHB is changed to the master state and assumes the responsibility for maintaining communication between the system resources and the I/O devices.Type: ApplicationFiled: December 8, 2014Publication date: April 2, 2015Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Jesse P. ARROYO, Srinivas KOTTA, Anjan Kumar GUTTAHALLI KRISHNA
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Publication number: 20150067297Abstract: DMA translation table entries include a consecutive count (CC) field that indicates how many subsequent translation table entries point to successive real page numbers. A DMA address translation mechanism stores a value in the CC field when a translation table entry is stored, and updates the CC field in other affected translation table entries as well. When a translation table entry is read, and the CC field is non-zero, the DMA controller can use multiple RPNs from the access to the single translation table entry. Thus, if a translation table entry has a value of 2 in the CC field, the DMA address translation mechanism knows it can access the real page number (RPN) corresponding to the translation table entry, and also knows it can access the two subsequent RPNs without the need of reading the next two subsequent translation table entries.Type: ApplicationFiled: April 14, 2014Publication date: March 5, 2015Applicant: International Business Machines CorporationInventors: Jesse P. Arroyo, Gregory M. Nordstrom, Srinivas Kotta, Eric N. Lais
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Publication number: 20150067224Abstract: DMA translation table entries include a consecutive count (CC) field that indicates how many subsequent translation table entries point to successive real page numbers. A DMA address translation mechanism stores a value in the CC field when a translation table entry is stored, and updates the CC field in other affected translation table entries as well. When a translation table entry is read, and the CC field is non-zero, the DMA controller can use multiple RPNs from the access to the single translation table entry. Thus, if a translation table entry has a value of 2 in the CC field, the DMA address translation mechanism knows it can access the real page number (RPN) corresponding to the translation table entry, and also knows it can access the two subsequent RPNs without the need of reading the next two subsequent translation table entries.Type: ApplicationFiled: August 29, 2013Publication date: March 5, 2015Applicant: International Business Machines CorporationInventors: Jesse P. Arroyo, Gregory M. Nordstrom, Srinivas Kotta, Eric N. Lais
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Publication number: 20150019903Abstract: Instead of disabling PCI communication between system resources in a host computing device and I/O devices when a PCI Host Bridge (PHB) is unable to function, the host computing device may include a redundant PCI communication path for maintaining communication between the system resources and the I/O devices after a first PHB experiences an unrecoverable error. In one embodiment, the redundant PCI communication path includes a second PHB that is maintained in a standby state so long as the first PHB is functioning normally. However, once the first PHB experiences an unrecoverable error, the second PHB is changed to the master state and assumes the responsibility for maintaining communication between the system resources and the I/O devices.Type: ApplicationFiled: July 12, 2013Publication date: January 15, 2015Inventors: Jesse P. ARROYO, Srinivas KOTTA, Anjam Kumar GUTTAHALLI KRISHNA