Abstract: An integrated circuit die stack is disclosed that includes a digital device layer, an underlying layer, and a cooling solution. The underlying layer has a lower power consumption relative to the digital device layer. The digital device layer is disposed closer to the cooling solution. In another example, memory layers and a digital device layer are configured into a three-dimensional memory stack. The digital device layer has a first surface (side) located closest to a cooling solution and the memory layers are located on a second surface (side) of the digital device layer opposite to the first surface (side) thereof. The cooling solution is adapted to receive and dissipate heat from the digital device layer and the memory layers.

Abstract: Efficient memory operation using a destructive read memory array is described. In accordance with the described techniques, a system may include a memory configured to store data of a first logic state in a ferroelectric capacitor when an electric polarization of the ferroelectric capacitor is in a first direction. A system may include a controller configured to erase the data from the memory by commanding the electric polarization of the ferroelectric capacitor in a second direction, opposite of the first direction and skipping a subsequent write operation of a null value to the memory.

Abstract: A disclosed semiconductor device includes (1) a silicon stack comprising a front-side Back-End-of-Line (BEOL) stack and a back side BEOL stack, the front-side BEOL stack comprising a plurality of signal routes and the back-side BEOL stack comprising a plurality of power delivery routes, and (2) a plurality of auxiliary power paths formed within the front-side BEOL stack and electrically coupled to the plurality of power delivery routes of the back-side BEOL stack via a plurality of programmable switches, the plurality of power delivery routes, the plurality of programmable switches, and the plurality of auxiliary power paths forming a programmable power delivery network (PDN). Various other apparatuses, systems, and methods of operation are also disclosed.

Abstract: In certain embodiments, the invention is directed to apparatus comprising a liquid-impregnated surface, said surface comprising an impregnating liquid and a matrix of solid features spaced sufficiently close to stably contain the impregnating liquid therebetween or therewithin, and methods thereof. In some embodiments, one or both of the following holds: (i) 0<??0.25, where ? is a representative fraction of the projected surface area of the liquid-impregnated surface corresponding to non-submerged solid at equilibrium; and (ii) Sow(a)<0, where Sow(a) is spreading coefficient, defined as ?wa??wo??oa, where ? is the interfacial tension between the two phases designated by subscripts w, a, and o, where w is water, a is air, and o is the impregnating liquid.

Abstract: An exemplary computing device includes a plurality of circuits and/or a plurality of in-situ monitors configured to generate outputs that indicate one or more operating conditions of the circuits. The computing device also includes a system management unit configured to detect a potentially faulty voltage-to-frequency ratio implemented by one of the circuits based at least in part on one or more of the outputs. The system management unit is also configured to modify the potentially faulty voltage-to-frequency ratio based at least in part on one or more of the outputs. Various other devices, systems, and methods are also disclosed.

Abstract: A process for preparing a Mn+4 doped phosphor of formula I Ax[MFy]:Mn+4 I includes combining a first solution comprising a source of A and a second solution comprising H2MF6 in the presence of a source of Mn, to form the Mn+4 doped phosphor; wherein A is Li, Na, K, Rb, Cs, or a combination thereof; M is Si, Ge, Sn, Ti, Zr, Al, Ga, In, Sc, Y, La, Nb, Ta, Bi, Gd, or a combination thereof; x is the absolute value of the charge of the [MFy] ion; y is 5, 6 or 7; and wherein a value of a Hammett acidity function of the first solution is at least ?0.9. Particles produced by the process may have a particle size distribution with a D50 particle size of less than 10 ?m.

Abstract: A process for preparing a Mn+4 doped phosphor of formula I Ax [MFy]:Mn+4 I includes combining a first solution comprising a source of A and a second solution comprising H2MF6 in the presence of a source of Mn, to form the Mn+4 doped phosphor; wherein A is Li, Na, K, Rb, Cs, or a combination thereof; M is Si, Ge, Sn, Ti, Zr, Al, Ga, In, Sc, Y, La, Nb, Ta, Bi, Gd, or a combination thereof; x is the absolute value of the charge of the [MFy] ion; y is 5, 6 or 7; and wherein a value of a Hammett acidity function of the first solution is at least ?0.9. Particles produced by the process may have a particle size distribution with a D50 particle size of less than 10 ?m.

Abstract: The invention relates to a processing system and corresponding method for processing image data and for indexing regions of interest in an object of interest. The system comprises a registration unit for registering the image data, a sub-volume generator generating sub-volumes from the image data, a composite image generator for generating multiple sets of composite images from each sub-volume, each set of composite images representing a different projection. The system comprises an indexing unit for generating indexed regions of interest in each sub-volume by assessing each of the set of composite images in parallel and a combining unit for combining each set of composite images of each sub-volume into a scan level prioritization.

Abstract: An exemplary computing device includes a plurality of circuits and/or a plurality of in-situ monitors configured to generate outputs that indicate one or more operating conditions of the circuits. The computing device also includes a system management unit configured to detect a potentially faulty voltage-to-frequency ratio implemented by one of the circuits based at least in part on one or more of the outputs. The system management unit is also configured to modify the potentially faulty voltage-to-frequency ratio based at least in part on one or more of the outputs. Various other devices, systems, and methods are also disclosed.

Abstract: A process for preparing a Mn+4 doped phosphor of formula I Ax[MFy]:Mn+4??I includes combining a first solution comprising a source of A and a second solution comprising H2MF6 in the presence of a source of Mn, to form the Mn+4 doped phosphor; wherein A is Li, Na, K, Rb, Cs, or a combination thereof; M is Si, Ge, Sn, Ti, Zr, Al, Ga, In, Sc, Y, La, Nb, Ta, Bi, Gd, or a combination thereof; x is the absolute value of the charge of the [MFy] ion; y is 5, 6 or 7; and wherein a value of a Hammett acidity function of the first solution is at least ?0.9. Particles produced by the process may have a particle size distribution with a D50 particle size of less than 10 ?m.

Abstract: Memory stacks having substantially vertical bitlines, and chip packages having the same, are disclosed herein. In one example, a memory stack is provided that includes a first memory IC die and a second memory IC die. The second memory IC die is stacked on the first memory IC die. Bitlines are routed through the first and second IC dies in a substantially vertical orientation. Wordlines within the first memory IC die are oriented orthogonal to the bitlines.

Abstract: Dynamic memory operations are described. In accordance with the described techniques, a system includes a stacked memory and one or more memory monitors configured to monitor conditions of the stacked memory. A system manager is configured to receive the monitored conditions of the stacked memory from the one or more memory monitors, and dynamically adjust operation of the stacked memory based on the monitored conditions. In one or more implementations, a system includes a memory and at least one register configured to store a ranking for each of a plurality of portions of the memory. Each respective ranking is determined based on an associated retention time of the respective portion of the memory. A memory controller is configured to dynamically refresh the portions of the memory at different times based on the ranking for each of the plurality of portions of the memory stored in the at least one register.

Abstract: Disclosed wherein stacked memory dies that utilize a mix of high and low operational temperature memory and non-volatile based memory dies, and chip packages containing the same. High temperature memory dies, such as those using non-volatile memory (NVM) technologies are in a memory stack with low temperature memory dies, such as those having volatile memory technologies. In some cases, the high temperature memory technologies could be used together, in some cases, on the same IC die as logic circuitry. In one example, a memory stack is provided that include a first memory IC die having high temperature memory circuitry, such as non-volatile memory, stacked below a second memory IC die. The second memory IC die has high temperature memory circuitry, such as volatile memory circuitry.

Abstract: A memory device includes memory cells. A memory cell of the memory cells includes gate circuitry, a first capacitor, and a second capacitor. The gate circuitry is connected to a wordline and a bitline. The first capacitor is connected to the gate circuitry and a first drive line. The second capacitor is connected to the gate circuitry and a second drive line.

Abstract: Error correction for stacked memory is described. In accordance with the described techniques, a system includes a plurality of error correction code engines to detect vulnerabilities in a stacked memory and coordinate at least one vulnerability detected for a portion of the stacked memory to at least one other portion of the stacked memory.

Abstract: A memory device includes a memory circuitry includes a first transmission grate, a first capacitor, a second transmission gate, and a second capacitor. The first transmission gate includes a first transistor connected between a first node and a second node. The first transistor having a gate terminal connected to a first clock node. The first clock node configured to receive a first clock signal. The first capacitor is connected between the second node and a first voltage node. The first capacitor is a ferroelectric capacitor. The second transmission gate includes a second transistor connected between the second node and a third node. The second transistor has a gate terminal connected to the first clock node. The second capacitor is connected between the third node and a second voltage node.

Abstract: According to one implementation of the present disclosure, a circuit structure is configured to store charge in a charge-based storage element, where the charge-based storage element is disposed at least partially in a shallow-trench-isolation (STI) region of the circuit. According to one implementation of the present disclosure, a method includes: providing a circuit structure disposed on a substrate and a shallow-trench-isolation (STI) region of a circuit; forming an opening of the substrate and the STI region by removing a portion of the substrate and STI region; placing a first liner material in the opening and on remaining portions of the substrate and the STI region; and depositing a first metal layer in the opening on the first liner material.

Abstract: Proposed concepts thus aim to provide schemes, solutions, concepts, designs, methods and systems pertaining to predicting a field perturbation map for magnetic resonance imaging (MRI) of a subject. In particular, the invention aims to provide a field perturbation map of the subject without the need for additional time-consuming scans of the subject. An accurate field perturbation map is necessary in order to obtain an MRI scan of the subject of high quality. Accordingly, a synthetic computed tomography (CT) image is generated by inputting an initial MRI magnitude image of the subject to an image conversion machine learning algorithm. Subsequently, a weighted susceptibility map of the subject is determined based on the synthetic CT image and the initial MRI magnitude image, which is in turn used to determine the field perturbation map of the subject.

Abstract: According to one implementation of the present disclosure, a cache memory includes: a plurality of cache-lines, wherein each row of cache-lines comprises: tag bits of a tag-random access memory (tag-RAM); data bits of a data-random access memory (data-RAM), and a single set of retention bits corresponding to the tag-RAM. According to one implementation of the present disclosure, a method includes: sampling a single set of retention bits of a cache-line of a cache memory, where the cache-line comprises the single set of retention bits, tag-RAM and data-RAM, and where at least the single set of retention bits comprise eDRAM bitcells; and performing a refresh cycle of at least the data-RAM corresponding to the tag-RAM based on the sampled single set of retention bits.

Abstract: A heat treatable decorative patterned glass article ha a selectively dissolvable coating. The selectively dissolvable coating is a silicon based monolayer optical coating which is intended to be selectively dissolved in regions underlying a patterned enamel coating during a processing operation of the transparent substrate. The decorative patterned glass article provides excellent contrast to the glass when viewed from the glass side and can withstand the high tempering temperatures during the making of the decorative glass article.