Abstract: A programmable logic device or field programmable gate array includes an on-chip clock synchronization circuit to synchronize a reference or system clock signal. The clock synchronization circuit is a delay-locked loop (DLL) circuit in one implementation and a phase locked loop (PLL) circuit in another implementation. The DLL or PLL circuits may be analog or digital. The clock synchronization circuit generates a synchronized clock signal that is distributed throughout the programmable integrated circuit. The synchronized clock signal is programmably connected to the programmable logic elements or logic array blocks (LABs) of the integrated circuit. The clock synchronization circuit reduces or minimizes clock skew when distributing a clock signal within the integrated circuit. The clock synchronization circuit improves the overall performance of the programmable logic integrated circuit.

Abstract: A programmable logic array integrated circuit is provided which comprises: a plurality of logic array blocks in which respective logic array blocks include, multiple respective programmable logic elements and respective random access memory arrays and corresponding memory access control circuitry and respective shared programmable local interfaces; and a network of conductors which is programmable to connect a respective local interface circuit of substantially any logic array block to a respective local interface of substantially any other logic array block.

Abstract: A programmable logic device architecture including tristate structures. The programmable logic device architecture provides tristate structures which may be logically or programmably controlled, or both. Through these tristate structures, the logic elements may be coupled to the programmable interconnect, where they may be coupled with other logic elements of the programmable logic device. Using these tristate structures, the signal pathways of the architecture may be dynamically reconfigured.

Abstract: A programmable logic device or field programmable gate array includes an on-chip clock synchronization circuit to synchronize a reference or system clock signal. The clock synchronization circuit is a delay-locked loop (DLL) circuit in one implementation and a phase-locked loop (PLL) circuit in another implementation. The DLL or PLL circuits may be analog or digital. The clock synchronization circuit generates a synchronized clock signal that is distributed throughout the programmable integrated circuit. The synchronized clock signal is programmably connected to the programmable logic elements or logic array blocks (LABs) of the integrated circuit. The clock synchronization circuit reduces or minimizes clock skew when distributing a clock signal within the integrated circuit. The clock synchronization circuit improves the overall performance of the programmable logic integrated circuit.

Abstract: A programmable logic device architecture incorporating a peripheral overflow bus is disclosed. In a preferred embodiment, the programmable logic device has a core region that includes at least a plurality of logic cells interconnected by way of associated programmable logic cell conductors. The interconnected logic cells form an array suitable for use in implementing desired logic functions. The programmable logic device also has a peripheral region. The peripheral region includes at least a plurality of bi-directional ports of which selected ones may be coupled to external circuitry. The peripheral region also includes a bi-directional peripheral I/O overflow bus suitably arranged to pass a plurality of control signals and a plurality of data signals between the core region and the plurality of bi-directional ports.

Abstract: An energy absorbing occupant restraint system for a motor vehicle includes a load-limiting buckle assembly. The buckle assembly includes a first elongated member adapted to be secured to the floor of the motor vehicle and a second elongated member. The buckle assembly further includes a buckle attached to the first elongated member. The buckle is adapted to releasably engage a tongue assembly carried by a seat belt webbing. A connector member interconnects the first and second elongated members. The second elongated member is configured so as to incrementally allow the second elongated member to translate relative to the first elongated member when the first elongated member is acted upon by a load which exceeds a predetermined level. In the preferred embodiment, the second elongated member is a sleeve member which telescopically receives the first elongated member.

Abstract: A system (100) for distributing a clock signal to many points on an integrated circuit. The system includes using a delay lock loop with specific digital circuits to accomplish the phase error detection and delay element selection. In one embodiment, two flip-flops are used to detect a phase error. In another embodiment, both macro (202) and micro phase detectors (218) are used and the delay element selection is performed in two stages by using a shift register (210) in a first stage and a counter (220) in a second stage. Another feature of the present invention is, the ability to distribute the reference clock or a synchronized clock to different portions of the circuitry on an integrated circuit. Multiple clock distribution systems are provided which may be selected.

Abstract: An improved multiplexer arrangement for connecting global conductors to logic array block (LAB) inputs. A single connection connects a particular global conductor to an input path to LABs on both sides of the interconnect region in a folded LAB architecture. The number of connections to the global conductors is thus reduced, reducing the number of transistors needed to make those connections and the corresponding loading of the global conductors. The connections to two paths are part of a first level multiplexer. A second-level multiplexer connected to each LAB line is also provided to add back some of the flexibility lost by having each global conductor connection connect to two paths. The invention cuts the number of transistors needed to connect to the global conductors in half, while adding some transistors for the second-level multiplexers, with a net reduction in connection transistors of about 1/3.

Abstract: A programmable logic device architecture including tristate structures. The programmable logic device architecture provides tristate structures which may be logically or programmably controlled, or both. Through these tristate structures, the logic elements may be coupled to the programmable interconnect, where they may be coupled with other logic elements of the programmable logic device. Using these tristate structures, the signal pathways of the architecture may be dynamically reconfigured.

Abstract: A hierarchical interconnect structure between logic elements, logic array blocks and global interconnects in a programmable logic device is disclosed. The present invention provides a first group of local interconnect lines that couple to outputs of more than one logic element in a block, and a second group of local interconnect lines that are divided into independent segments coupled to a subset of the logic elements in a block. By eliminating the one-to-one correspondence between the number of logic elements in a logic array block and the number of local interconnect wires, the present invention makes possible the inclusion of more logic element in one block in an area efficient manner.

Abstract: A system (100) for distributing a clock signal to many points on an integrated circuit. The system includes using a delay lock loop with specific digital circuits to accomplish the phase error detection and delay element selection. In one embodiment, two flip-flops are used to detect a phase error. In another embodiment, both macro (202) and micro phase detectors (218) are used and the delay element selection is performed in two stages by using a shift register (210) in a first stage and a counter (220) in a second stage. Another feature of the present invention is, the ability to distribute the reference clock or a synchronized clock to different portions of the circuitry on an integrated circuit. Multiple clock distribution systems are provided which may be selected.