Abstract: A programmable logic array integrated circuit has several regular columns of programmable logic circuitry and a spare column which includes a subset of the programmable logic circuitry that is included in a regular column. In the event of a defect in the circuitry in a regular column that is duplicated in the spare column, the regular column logic functions that are thus duplicated are shifted from column to column so that the spare column circuitry is put to use and the defective regular column circuitry is not used. Regular column functions that are not duplicated in the spare column are not shifted. Data for programming the columns is selectively routed to the columns with or without column shifting, depending on whether that data is for functions that are or are not duplicated in the spare column.

Abstract: Programmable logic array devices are programmed from programming devices in networks that facilitate programming any number of such logic devices with programs of any size or complexity. The source of programming data and control may be a microprocessor or one or more serial EPROMs, one EPROM being equipped with a clock circuit. Several parallel data streams may be used to speed up the programming operation. A clock circuit with a programmably variable speed may be provided to facilitate programming logic devices with different speed characteristics. The programming protocol may include an acknowledgement from the logic device(s) to the programming data source after each programming data transmission so that the source can automatically transmit programming data at the speed at which the logic device is able to accept that data.

Abstract: An improved architecture and method of operation for providing redundancy in programmable logic devices. Spare columns or rows of logic blocks 115 and switch boxes 140 are employed to replace columns or rows of logic blocks containing one or more defective logic blocks. Associated logic enable the device to bypass a column or row of logic blocks 115 containing one or more defective logic blocks 115 and to switch in a spare column or row of defect-free logic blocks 115 as replacement.

Abstract: A programmable, integrated circuit, logic array device has several regular logic groups and at least one spare logic group. If any of the regular logic groups is defective, the spare logic group is used to make up for the defective logic group. To accomplish this, programming and data input signals that would normally go to the defective logic group are redirected to another logic group. The data output signals of the other group are substituted for the data output signals of the logic group that would normally have received the programming and data input signals that were redirected to the other logic group.

Abstract: A look-up table circuit implemented with MOS transistors that uses combinational logic to generate signals that enable the transistors. A circuit using 16 inputs and 4 select lines is disclosed. Two of the select lines are used as inputs to combinational logic including four NOR gates to generate enable signals for transistors in a third stage of the circuit. This produces a reduction in the propagation delay of a signal from the input to the output of the look-up table circuit.

Abstract: A programmable, integrated circuit, logic array device has several regular logic groups and at least one spare logic group. If any of the regular logic groups is defective, the spare logic group is used to make up for the defective logic group. To accomplish this, programming and data input signals that would normally go to the defective logic group are redirected to another logic group. The data output signals of the other group are substituted for the data output signals of the logic group that would normally have received the programming and data input signals that were redirected to the other logic group.

Abstract: A voltage translation circuit 6 and method of operating a circuit to provide voltage level translation, particularly for use in association with a programmable logic device 2. An input signal, is provided to an NMOS transistor N2 and a CMOS inverter 12. The inverter 12 drives an NMOS pulldown transistor N4. The drain of N2 is coupled to the input of an inverter 14, the output of which is also coupled to the translation circuit output. A source of PMOS pullup transistor P1 drives the input of inverter 14 to pullup the output to a high level.

Abstract: The output buffer includes first and second N channel FETs serially connected between a ground terminal and a voltage supply terminal and having a common terminal connected to an output terminal. Third and fourth N channel FETs are serially connected between the ground terminal and the voltage supply terminal and have a common terminal connected to the output terminal. A first logic circuit responds to data input (DIN) signals and an operation enable bar (OEB) signal for applying a conductive bias voltage to the third N channel FET, and a second logic circuit responds to the DIN signals and the OEB signal for applying a conductive bias voltage to the fourth N channel FET. A first P channel FET couples the conductive bias voltage on the third N channel FET to the first N channel FET, and a second P channel FET couples the conductive bias on the fourth N channel FET to the second N channel FET.