Patents by Inventor Srinivasan Dasasathyan

Srinivasan Dasasathyan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240193341
    Abstract: Placement of macros of a circuit design includes mapping the macros to types of sub-circuits of an integrated circuit (IC). The IC includes anchors and instances of each type of the types of sub-circuits. The macros are grouped based on couplings of the macros to the anchors specified in the circuit design. Each group includes one or more macros, and the one or more macros in each group are all coupled to the same set of one or more anchors. A location is selected from alternative locations for each group of macros based on a distance of the location from the same set of anchors. Each location includes one or more instances of one or more types of the types of sub-circuits. The circuit design is placed and routed after selecting the location for each group, and implementation data is generated for making an IC that implements the circuit design.
    Type: Application
    Filed: December 9, 2022
    Publication date: June 13, 2024
    Applicant: Xilinx, Inc.
    Inventors: Veeresh Pratap Singh, Mohit Sharma, Chatla Surya Phanindra, Sandip Maity, Aman Gayasen, Srinivasan Dasasathyan
  • Publication number: 20240111932
    Abstract: Multiple classifier models are applied to features of a circuit design after processing the design through a first phase of an implementation flow. Each classifier model is associated with one of multiple directives, the directives are associated with a second phase of the implementation flow, and each classifier model returns a value indicative of likelihood of improving a quality metric. Regressor models of each set of a plurality of sets of regressor models are applied to the features. Each directive is associated with one of the sets of regressor models, and a combined score from each set of regressor models indicates a likelihood of satisfying a constraint. The directives are ranked based on the values indicated by the classifier models and scores from the sets of regressor models, and the circuit design is processed n the second phase of the implementation flow by the design tool using the directive having the highest rank.
    Type: Application
    Filed: October 3, 2022
    Publication date: April 4, 2024
    Applicant: Xilinx, Inc.
    Inventors: Satish Bachina, Karthic P, Vishal Tripathi, Srinivasan Dasasathyan
  • Patent number: 11714950
    Abstract: Processing a circuit design includes stabilizing the circuit design by a design tool that performs one or more iterations of implementation, optimization assessment, optimization, and stability assessment until a threshold stability level is achieved. The design tool determines, in response to satisfaction of the threshold stability level, different strategies based on features of the circuit design and likelihood that use of the strategies would improve timing. Each strategy includes parameter settings for the design tool. The design tool executes multiple implementation flows using different sets of strategies to generate alternative implementations. One implementation of the alternative implementations nearest to satisfying a timing requirement is selected.
    Type: Grant
    Filed: July 22, 2021
    Date of Patent: August 1, 2023
    Assignee: XILINX, INC.
    Inventors: Veeresh Pratap Singh, Meghraj Kalase, John Blaine, Srinivasan Dasasathyan, Padmini Gopalakrishnan, Frederic Revenu, Veena Johar, Pawan Kumar Singh, Mohit Sharma, Kameshwar Chandrasekar
  • Patent number: 11586791
    Abstract: Approaches for visualizing data buses in a circuit design include determining ones of the data buses that satisfy selection criteria. For each element connected to a data bus of the ones of the data buses, a method and system determine whether the element is of interest or the element is not of interest. A graphical representation of the ones of the data buses and each element of interest is generated, and data buses of the circuit design determined to not satisfy the selection criteria and elements not of interest are excluded from the graphical representation. The graphical representation is displayed on a display device.
    Type: Grant
    Filed: September 21, 2021
    Date of Patent: February 21, 2023
    Assignee: XILINX, INC.
    Inventors: Anup Hosangadi, Aman Gayasen, Srinivasan Dasasathyan, Padmini Gopalakrishnan
  • Publication number: 20230034736
    Abstract: Processing a circuit design includes stabilizing the circuit design by a design tool that performs one or more iterations of implementation, optimization assessment, optimization, and stability assessment until a threshold stability level is achieved. The design tool determines, in response to satisfaction of the threshold stability level, different strategies based on features of the circuit design and likelihood that use of the strategies would improve timing. Each strategy includes parameter settings for the design tool. The design tool executes multiple implementation flows using different sets of strategies to generate alternative implementations. One implementation of the alternative implementations nearest to satisfying a timing requirement is selected.
    Type: Application
    Filed: July 22, 2021
    Publication date: February 2, 2023
    Applicant: Xilinx, Inc.
    Inventors: Veeresh Pratap Singh, Meghraj Kalase, John Blaine, Srinivasan Dasasathyan, Padmini Gopalakrishnan, Frederic Revenu, Veena Johar, Pawan Kumar Singh, Mohit Sharma, Kameshwar Chandrasekar
  • Patent number: 11003826
    Abstract: Strategies are stored in a memory arrangement, and each strategy includes a set of parameter settings for a design tool. The design tool identifies a set of features of an input circuit design and applies classification models to the input circuit design. Each classification model indicates one the strategies, and application of each classification model indicates a likelihood that use of the strategy would improve a metric of the input circuit design based on the set of features of the input circuit design. One strategy of the plurality of strategies is selected based on the likelihood that use of the one strategy would improve the metric of the input circuit design, and the design tool is configured with the set of parameter settings of the one strategy. The design tool then processes the input circuit design into implementation data that is suitable for making an integrated circuit (IC).
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: May 11, 2021
    Assignee: XILINX, INC.
    Inventors: Srinivasan Dasasathyan, Padmini Gopalakrishnan, Vishal Tripathy, Vikas N. Vedamurthy, Sumit Nagpal
  • Patent number: 10867093
    Abstract: Disclosed approaches for guiding actions in processing a circuit design include a design tool identifying first violations of design checks and determining severity levels of the first violations. The design tool determines for each violation, suggested actions associated with the violation and presents on a display, first data indicative of the suggested actions in order of the severity levels of the first violations. The first data include selectable objects, and each selectable object has an associated executable procedure. The design tool can execute the procedure associated with one of the selectable objects in response to selection and modify the circuit design in response to execution of the procedure.
    Type: Grant
    Filed: March 20, 2019
    Date of Patent: December 15, 2020
    Assignee: Xilinx, Inc.
    Inventors: John Blaine, Srinivasan Dasasathyan, Meghraj Kalase, Frederic Revenu, Veeresh Pratap Singh, Satish Bachina, Shail Bains, Padmini Gopalakrishnan, Sumit Nagpal, Gaurav Dutt Sharma
  • Patent number: 9501604
    Abstract: A method of testing a circuit design includes generating, for each net of each critical path in the circuit design, a respective ring oscillator circuit design. The ring oscillator circuit design has a source gate coupled to a destination gate via the net and a feedback path that couples an output pin of the destination gate to an input pin of the source gate. Configuration data are generated to implement a respective ring oscillator circuit from each ring oscillator circuit design, and a programmable integrated circuit is configured with the configuration data. The method determines a delay of the net of each ring oscillator circuit.
    Type: Grant
    Filed: September 23, 2014
    Date of Patent: November 22, 2016
    Assignee: XILINX, INC.
    Inventors: Geetesh More, Srinivasan Dasasathyan, Nagaraj Savithri
  • Patent number: 8473881
    Abstract: A method of partitioning a circuit design can include identifying a circuit design in which components of the circuit design are assigned to each of a plurality of regions, wherein each region corresponds to a physical portion of an integrated circuit. A maximum oversubscription region can be determined for a selected component type from the plurality of regions. A target region from the plurality of regions can be selected that is adjacent to the region of maximum oversubscription. The method also can include re-assigning, by a processor, a selected number of components of the maximum oversubscription region to the target region.
    Type: Grant
    Filed: January 17, 2011
    Date of Patent: June 25, 2013
    Assignee: Xilinx, Inc.
    Inventors: Wei Mark Fang, Vishal Suthar, Srinivasan Dasasathyan
  • Patent number: 8448122
    Abstract: A method of implementing a circuit design within a programmable integrated circuit (IC) can include identifying an implementation directive embedded within a register transfer level (RTL) description of the circuit design and determining components of a sub-circuit of the circuit design, wherein the sub-circuit is specified by a portion of the RTL description associated with the implementation directive. The sub-circuit can be placed for the programmable IC and routed for the programmable IC according to the implementation directive. A programmatic description of the sub-circuit specifying placement and routing information can be output.
    Type: Grant
    Filed: April 1, 2009
    Date of Patent: May 21, 2013
    Assignee: Xilinx, Inc.
    Inventors: Vishal Suthar, Hasan Arslan, Sridhar Krishnamurthy, Sanjeev Kwatra, Srinivasan Dasasathyan, Rajat Aggarwal, Sudip K. Nag
  • Patent number: 8418115
    Abstract: A method of component placement for a multi-die integrated circuit (IC) can include partitioning a plurality of components of a netlist among a plurality of dies of the multi-die IC and selecting a superimposition model specifying a positioning of at least two of the plurality of dies at least partially superimposed with respect to one another. The method also can include assigning, by a processor, components of the netlist to hardware units within each of the plurality of dies according, at least in part, to a wire-length metric calculated using the superimposition model.
    Type: Grant
    Filed: May 11, 2010
    Date of Patent: April 9, 2013
    Assignee: Xilinx, Inc.
    Inventors: Marvin Tom, Rajat Aggarwal, Srinivasan Dasasathyan
  • Patent number: 8312405
    Abstract: A method of placing input/output blocks on an integrated circuit device is described. The method may comprise receiving a circuit design having a plurality of input/output blocks to be placed at input/output sites of the integrated circuit device; modifying, for each input/output block of the circuit design, an input/output standard for the input/output block to include bus information; assigning, for each input/output block of the circuit design, an input/output site for the input/output block; and generating an input/output placement for the input/output blocks of the circuit design. A computer product is also disclosed.
    Type: Grant
    Filed: January 20, 2009
    Date of Patent: November 13, 2012
    Assignee: Xilinx, Inc.
    Inventors: Victor Slonim, Rajat Aggarwal, Guenter Stenz, Srinivasan Dasasathyan
  • Patent number: 8230377
    Abstract: A computer-implemented method of globally placing a circuit design on a programmable integrated circuit (IC) includes dividing, by a placement system, the programmable IC into a grid comprising a plurality of cells, assigning each component of a selected component type of the circuit design to one of a plurality of control set groups according to a control set of the component, and calculating a force including a control set force that depends upon overlap of control sets within the plurality of cells. The method further can include applying the force to at least one selected component of the circuit design and assigning components of the circuit design to locations on the programmable IC by solving a set of linear equations that depend upon application of the force to the at least one selected component to create a global placement. The circuit design including the global placement can be output.
    Type: Grant
    Filed: April 24, 2009
    Date of Patent: July 24, 2012
    Assignee: Xilinx, Inc.
    Inventors: Wei Mark Fang, Srinivasan Dasasathyan
  • Patent number: 8225262
    Abstract: A method of placing clock circuits in an integrated circuit is disclosed. The method comprises receiving a circuit design to be implemented in the integrated circuit; identifying portions of the circuit design comprising clock circuits; determining an order of clock circuits to be placed based upon resource requirements of the clock circuits; and placing the portions of the circuit design comprising clock circuits in sites of the integrated circuit. A system for placing clock circuits in an integrated circuit is also disclosed.
    Type: Grant
    Filed: March 18, 2009
    Date of Patent: July 17, 2012
    Assignee: Xilinx, Inc.
    Inventors: Marvin Tom, Wei Mark Fang, Srinivasan Dasasathyan
  • Patent number: 8091060
    Abstract: A computer-implemented method of partitioning a circuit design into clock domains for implementation within a programmable integrated circuit (IC) can include storing a plurality of constraints that depend upon a plurality of variables, wherein the plurality of constraints regulate placement of components to different clock regions of the programmable IC. The method can include storing an objective function and determining a result indicating whether a feasible solution exists for clock domain partitioning of the circuit design by minimizing the objective function subject to the plurality of constraints. The result can be output.
    Type: Grant
    Filed: February 10, 2009
    Date of Patent: January 3, 2012
    Assignee: Xilinx, Inc.
    Inventors: Marvin Tom, Srinivasan Dasasathyan
  • Patent number: 7735039
    Abstract: Methods of estimating delays between pins on a tile-based programmable logic device (PLD), by identifying repeat patterns and exploiting these patterns to provide accurate delay estimates. A computer-implemented method can include selecting a sample area in a tile-based PLD and constructing a delay table corresponding to the sample area. Each entry in the delay table includes a base delay value and a description of the fastest available route from a source pin in a source tile to a load pin in the sample area. To estimate a net delay, the base delay value and the description of the route are read from the delay table for specified source and load pins. One or more delay variants (e.g., pin delays and/or crossing penalties) are calculated based on the description of the route. The calculated delay variants are added to the base delay value to obtain an adjusted delay value, which is output.
    Type: Grant
    Filed: August 28, 2007
    Date of Patent: June 8, 2010
    Assignee: Xilinx, Inc.
    Inventors: Srinivasan Dasasathyan, Hasan Arslan, Meng Lou, Anirban Rahut
  • Patent number: 7636876
    Abstract: A method of placing a circuit design can include selecting one or more candidate mobile nodes from a plurality of overlapped nodes of the circuit design and determining a gain region for each candidate mobile node. The method also can include assigning the candidate mobile node to a site within a gain region according to a cost function. The gain region is associated with the candidate mobile node. The method further can include iteratively selecting and assigning candidate mobile nodes according to a measure of overlap for the circuit design.
    Type: Grant
    Filed: April 18, 2006
    Date of Patent: December 22, 2009
    Assignee: Xilinx, Inc.
    Inventors: Sankaranarayanan Srinivasan, Srinivasan Dasasathyan
  • Patent number: 7392499
    Abstract: Approaches for placing a plurality of input/output blocks (IOBs) of an electronic design in an integrated circuit are disclosed. The electronic design includes at least one input/output bus associated with a plurality of the IOBs, and the IOBs for each input/output bus are assigned to respective sets. For each combination of pairs of the sets a respective weight factor is generated to indicate a degree of coupling between the first and second sets in the electronic design. An order of the sets is generated, and the sets are placed in an ordered series of input/output sites in the integrated circuit according to the order of the sets. A cost function is evaluated for the pairs of the sets. The generating of the order of the sets and the placing of the sets is conditionally repeated responsive to the evaluating of the cost function.
    Type: Grant
    Filed: August 2, 2005
    Date of Patent: June 24, 2008
    Assignee: Xilinx, Inc.
    Inventors: Guenter Stenz, Srinivasan Dasasathyan
  • Patent number: 7313778
    Abstract: A method (600) of designing a programmable logic device can include the steps of identifying a cost function that penalizes floorplans of a circuit design that do not fit on the programmable logic device (605) and defining modules having components of a same type (615). A set of shapes associated with a module can be determined (610). The circuit design can be annealed (620) to determine a floorplan using the cost function and the set of shapes for the module.
    Type: Grant
    Filed: February 26, 2004
    Date of Patent: December 25, 2007
    Assignee: Xilinx, Inc.
    Inventors: Guenter Stenz, Srinivasan Dasasathyan, Rajat Aggarwal, James L. Saunders
  • Patent number: 7240315
    Abstract: A method (500) of placing local clock nets in a circuit design can include identifying the local clock nets for the circuit design and selecting components corresponding to each local clock net (510,515), and assigning initial locations to each component of the local clock nets (520). The method further can include generating at least one cost function (530, 550) to evaluate (555) different placements of components of the local clock nets. The components (220, 240) of the local clock nets (205) can be annealed (535–575) using one or more of the cost functions to assign locations to each component of the local clock nets.
    Type: Grant
    Filed: August 29, 2003
    Date of Patent: July 3, 2007
    Assignee: Xilinx, Inc.
    Inventors: Qiang Wang, Sudip K. Nag, Srinivasan Dasasathyan, James L. Saunders, Pavanish Nirula