Patents by Inventor Srinivasan Dasasathyan

Srinivasan Dasasathyan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method, system, and apparatus for incremental design in programmable logic devices using floorplanning
    Patent number: 7149993
    Abstract: A method of designing a programmable logic device can include receiving a modification to a programmable logic device that has been floorplanned. Modules of the programmable logic device that have been changed by the modification can be identified. The changed modules can be floorplanned thereby determining a placement solution that does not violate boundaries of unchanged modules. The programmable logic device then can be placed and routed.
    Type: Grant
    Filed: March 29, 2004
    Date of Patent: December 12, 2006
    Assignee: Xilinx, Inc.
    Inventors: Rajat Aggarwal, Guenter Stenz, Srinivasan Dasasathyan
  • Method for application of network flow techniques under constraints
    Patent number: 7143380
    Abstract: Application of network flow techniques to constrained optimization problems is disclosed. The present of constrains may lead to infeasible solutions. The infeasible solutions can be removed by an iterative process of changing the structure of the network and/or the associated parameters. Specific applications of the invention to the placement of tristate buffers and clocks in integrated circuits are disclosed.
    Type: Grant
    Filed: August 8, 2002
    Date of Patent: November 28, 2006
    Assignee: Xilinx, Inc.
    Inventors: Jason H. Anderson, Sudip K. Nag, Guenter Stenz, Srinivasan Dasasathyan
  • Placement of objects with partial shape restriction
    Patent number: 6857115
    Abstract: Application of network flow techniques to constrained optimization problems is disclosed. The present of constrains may lead to infeasible solutions. The infeasible solutions can be removed by an iterative process of changing the structure of the network and/or the associated parameters. Specific applications of the invention to the placement of tristate buffers and clocks in integrated circuits are disclosed.
    Type: Grant
    Filed: August 8, 2002
    Date of Patent: February 15, 2005
    Assignee: Xilinx, Inc.
    Inventors: Srinivasan Dasasathyan, Guenter Stenz, Sudip K. Nag, Jason H. Anderson
  • Placement of clock objects under constraints
    Patent number: 6789244
    Abstract: Application of network flow techniques to constrained optimization problems is disclosed. The present of constrains may lead to infeasible solutions. The infeasible solutions can be removed by an iterative process of changing the structure of the network and/or the associated parameters. Specific applications of the invention to the placement of tristate buffers and clocks in integrated circuits are disclosed.
    Type: Grant
    Filed: August 8, 2002
    Date of Patent: September 7, 2004
    Assignee: Xilinx, Inc.
    Inventors: Srinivasan Dasasathyan, Guenter Stenz, Sudip K. Nag