Patents by Inventor Srirama Chandra
Srirama Chandra has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11971992Abstract: Systems and methods for failure characterization of secure programmable logic devices (PLDs) are disclosed. An example system includes a secure PLD including programmable logic blocks (PLBs) arranged in PLD fabric of the secure PLD, and a configuration engine configured to program the PLD fabric according to a configuration image stored in non-volatile memory (NVM) of the secure PLD and/or coupled through a configuration input/output (I/O) of the secure PLD. The secure PLD is configured to receive a failure characterization (FC) command from the PLD fabric or an external system coupled to the secure PLD through the configuration I/O, and to execute the FC command to, at least in part, erase and/or nullify portions of the NVM. The secure PLD may also be configured to boot a debug configuration for the PLD fabric that identifies and/or characterizes operational failures of the secure PLD.Type: GrantFiled: November 9, 2020Date of Patent: April 30, 2024Assignee: Lattice Semiconductor CorporationInventors: Fulong Zhang, Srirama Chandra, Sreepada Hegade, Joel Coplen, Wei Han, Yu Sun
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Patent number: 11914716Abstract: Systems and methods for asset management for secure programmable logic devices (PLDs) are disclosed. An example system includes a secure PLD including programmable logic blocks (PLBs) arranged in PLD fabric of the secure PLD, and a configuration engine configured to program the PLD fabric according to a configuration image stored in non-volatile memory (NVM) of the secure PLD and/or coupled through a configuration input/output (I/O) of the secure PLD. The secure PLD is configured to receive a secure PLD asset access request from the PLD fabric or an external system coupled to the secure PLD through the configuration I/O, and to perform a secure PLD asset update process corresponding to the secure PLD asset access request, where the performing the asset update process is based on a lock status associated with a secure PLD asset corresponding to the secure PLD asset access request.Type: GrantFiled: November 9, 2020Date of Patent: February 27, 2024Assignee: Lattice Semiconductor CorporationInventors: Fulong Zhang, Srirama Chandra, Sreepada Hegade, Joel Coplen, Wei Han, Yu Sun
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Publication number: 20230315913Abstract: Various techniques are provided to implement multi-chip secure and programmable systems and methods. In one example, a multi-chip module system for providing an integrated programmable logic functionality and security functionality. The multi-chip module system includes a first die including a programmable logic device (PLD) configured to provide at least a portion of the programmable logic functionality. The multi-chip system further includes a second die including a security engine configured to perform at least a portion of the security functionality. The security engine is further configured to receive, from the first die, data associated with a first and second configuration image; perform a read operation on a memory for the second configuration image based on the data; and authenticate the second configuration image. The multi-chip system further includes a configuration engine configured to program the PLD according to the first configuration image. Related devices and methods are provided.Type: ApplicationFiled: June 7, 2023Publication date: October 5, 2023Inventors: Srirama Chandra, Tim Vogt, Mamta Gupta, Sharath Raghava
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Publication number: 20230145743Abstract: A classification system is provided that separates unclassified pages into unclassified, separated documents and classifies the separated documents. The classification system applies a page-level recognition model to the unclassified pages to recognize the logical boundaries between documents and, based on the logical boundaries, separates the pages into unclassified, separated documents. The classification system further applies a document-level recognition model to classify the separated documents.Type: ApplicationFiled: January 2, 2023Publication date: May 11, 2023Inventors: Sangeetha Yanamandra, Srirama Chandra Akella, Satish Chandra Paled, Newton Isaac Rajkumar
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Patent number: 11544947Abstract: A classification system is provided that separates unclassified pages into unclassified, separated documents and classifies the separated documents. The classification system applies a page-level recognition model to the unclassified pages to recognize the logical boundaries between documents and, based on the logical boundaries, separates the pages into unclassified, separated documents. The classification system further applies a document-level recognition model to classify the separated documents.Type: GrantFiled: May 25, 2021Date of Patent: January 3, 2023Assignee: OPEN TEXT SA ULCInventors: Sangeetha Yanamandra, Srirama Chandra Akella, Satish Chandra Paled, Newton Isaac Rajkumar
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Patent number: 11295492Abstract: An electronic device associated with rendering of web content, a server, and a controlling method thereof are provided. The controlling method includes receiving a request for the web content from an electronic device by the server executing a program for a content renderer, generating a render structure associated with render commands by the server executing the program for the content renderer, and sending, by the server executing the program for the content renderer, the render structure to the electronic device to render the web content, and the render commands are issued to each layer of a rendering engine to render the web content of the electronic device.Type: GrantFiled: July 29, 2016Date of Patent: April 5, 2022Assignee: Samsung Electronics Co., Ltd.Inventors: Naveen Kumar S G, Pruthvi Kumar Madugundu, Srirama Chandra Sekhar Mogali, Joy Bose
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Publication number: 20210286992Abstract: A classification system is provided that separates unclassified pages into unclassified, separated documents and classifies the separated documents. The classification system applies a page-level recognition model to the unclassified pages to recognize the logical boundaries between documents and, based on the logical boundaries, separates the pages into unclassified, separated documents. The classification system further applies a document-level recognition model to classify the separated documents.Type: ApplicationFiled: May 25, 2021Publication date: September 16, 2021Inventors: Sangeetha Yanamandra, Srirama Chandra Akella, Satish Chandra Paled
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Patent number: 11030446Abstract: A classification system is provided that separates unclassified pages into unclassified, separated documents and classifies the separated documents. The classification system applies a page-level recognition model to the unclassified pages to recognize the logical boundaries between documents and, based on the logical boundaries, separates the pages into unclassified, separated documents. The classification system further applies a document-level recognition model to classify the separated documents.Type: GrantFiled: June 11, 2019Date of Patent: June 8, 2021Assignee: Open Text SA ULCInventors: Sangeetha Yanamandra, Srirama Chandra Akella, Satish Chandra Paled, Newton Isaac Rajkumar
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Publication number: 20210081578Abstract: Systems and methods for failure characterization of secure programmable logic devices (PLDs) are disclosed. An example system includes a secure PLD including programmable logic blocks (PLBs) arranged in PLD fabric of the secure PLD, and a configuration engine configured to program the PLD fabric according to a configuration image stored in non-volatile memory (NVM) of the secure PLD and/or coupled through a configuration input/output (I/O) of the secure PLD. The secure PLD is configured to receive a failure characterization (FC) command from the PLD fabric or an external system coupled to the secure PLD through the configuration I/O, and to execute the FC command to, at least in part, erase and/or nullify portions of the NVM. The secure PLD may also be configured to boot a debug configuration for the PLD fabric that identifies and/or characterizes operational failures of the secure PLD.Type: ApplicationFiled: November 9, 2020Publication date: March 18, 2021Inventors: Fulong Zhang, Srirama Chandra, Sreepada Hegade, Joel Coplen, Wei Han, Yu Sun
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Publication number: 20210081536Abstract: Systems and methods for secure booting of secure programmable logic devices (PLDs) are disclosed. An example system includes a secure PLD including programmable logic blocks (PLBs) arranged in a PLD fabric of the secure PLD, and a configuration engine configured to program the PLD fabric according to a configuration image stored in a non-volatile memory (NVM) of the secure PLD and/or coupled through a configuration input/output (I/O) of the secure PLD to the configuration engine. The secure PLD is configured to retrieve a pre-authentication status associated with the configuration image from the NVM, determine or verify the retrieved pre-authentication status associated with the configuration image includes a valid status, and boot the PLD fabric of the secure PLD using the configuration image.Type: ApplicationFiled: November 9, 2020Publication date: March 18, 2021Inventors: Fulong Zhang, Srirama Chandra, Sreepada Hegade, Joel Coplen, Wei Han, Yu Sun
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Publication number: 20210083675Abstract: Systems and methods for provisioning secure programmable logic devices (PLDs) are disclosed. An example secure PLD provisioning system includes an external system comprising a processor and a memory and configured to be coupled to a secure PLD through a configuration input/output (I/O) of the secure PLD. The external system is configured to generate a locked PLD comprising the secure PLD based, at least in part, on a request from a secure PLD customer, wherein the request from the secure PLD customer comprises a customer public key; and to provide a secured unlock package for the locked secure PLD. The external system may also be configured to provide an authenticatable key manifest comprising a customer programming key token and a corresponding programming public key associated with the locked secure PLD, wherein the authenticatable key manifest is signed using a programming private key generated by the locked secure PLD.Type: ApplicationFiled: November 9, 2020Publication date: March 18, 2021Inventors: Srirama Chandra, Fulong Zhang, Sreepada Hegade, Joel Coplen, Wei Han, Yu Sun
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Publication number: 20210081577Abstract: Systems and methods for asset management for secure programmable logic devices (PLDs) are disclosed. An example system includes a secure PLD including programmable logic blocks (PLBs) arranged in PLD fabric of the secure PLD, and a configuration engine configured to program the PLD fabric according to a configuration image stored in non-volatile memory (NVM) of the secure PLD and/or coupled through a configuration input/output (I/O) of the secure PLD. The secure PLD is configured to receive a secure PLD asset access request from the PLD fabric or an external system coupled to the secure PLD through the configuration I/O, and to perform a secure PLD asset update process corresponding to the secure PLD asset access request, where the performing the asset update process is based on a lock status associated with a secure PLD asset corresponding to the secure PLD asset access request.Type: ApplicationFiled: November 9, 2020Publication date: March 18, 2021Inventors: Fulong Zhang, Srirama Chandra, Sreepada Hegade, Joel Coplen, Wei Han, Yu Sun
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Publication number: 20200394396Abstract: A classification system is provided that separates unclassified pages into unclassified, separated documents and classifies the separated documents. The classification system applies a page-level recognition model to the unclassified pages to recognize the logical boundaries between documents and, based on the logical boundaries, separates the pages into unclassified, separated documents. The classification system further applies a document-level recognition model to classify the separated documents.Type: ApplicationFiled: June 11, 2019Publication date: December 17, 2020Inventors: Sangeetha Yanamandra, Srirama Chandra Akella, Satish Chandra Paled, Newton Isaac Rajkumar
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Patent number: 10754401Abstract: In one embodiment, a reconfigurable and scalable hardware management architecture includes a digital controller for controlling two or more analog sense-and-control (ASC) circuits, where each ASC monitors voltage, current, and temperature of one or more power supplies, ICs, or a circuit board. The controller and ASCs are connected in a star architecture, where each ASC is connected to the controller via a different, dedicated interface to communicate regarding the power supplies being monitored. The controller and the ASCs are also connected in a bus architecture via a shared interface. The architecture can be re-configured by adding one or more additional ASCs or by removing one or more existing ASCs, where each additional ASC is (i) connected to a different I/O interface of the digital controller via a different, dedicated interface and (ii) connected to the digital controller and the two or more existing ASCs via the shared interface.Type: GrantFiled: May 20, 2019Date of Patent: August 25, 2020Assignee: LATTICE SEMICONDUCTOR CORPORATIONInventors: Srirama Chandra, Robert Bartel
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Publication number: 20190272010Abstract: In one embodiment, a reconfigurable and scalable hardware management architecture includes a digital controller for controlling two or more analog sense-and-control (ASC) circuits, where each ASC monitors voltage, current, and temperature of one or more power supplies, ICs, or a circuit board. The controller and ASCs are connected in a star architecture, where each ASC is connected to the controller via a different, dedicated interface to communicate regarding the power supplies being monitored. The controller and the ASCs are also connected in a bus architecture via a shared interface. The architecture can be re-configured by adding one or more additional ASCs or by removing one or more existing ASCs, where each additional ASC is (i) connected to a different I/O interface of the digital controller via a different, dedicated interface and (ii) connected to the digital controller and the two or more existing ASCs via the shared interface.Type: ApplicationFiled: May 20, 2019Publication date: September 5, 2019Inventors: Srirama Chandra, Robert Bartel
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Patent number: 10296061Abstract: In one embodiment, a reconfigurable and scalable hardware management architecture includes a digital controller for controlling two or more analog sense-and-control (ASC) circuits, where each ASC monitors voltage, current, and temperature of one or more power supplies (e.g., DC-to-DC converters), ICs, or a circuit board. The controller and ASCs are connected in a star architecture, where each ASC is connected to the controller via a different, dedicated interface to communicate regarding the power supplies being monitored. In addition, the controller and the ASCs are also connected in a bus architecture via a shared interface. The architecture can be re-configured by adding one or more additional ASCs or by removing one or more existing ASCs, where each additional ASC is (i) connected to a different I/O interface of the digital controller via a different, dedicated interface and (ii) connected to the digital controller and the two or more existing ASCs via the shared interface.Type: GrantFiled: December 19, 2014Date of Patent: May 21, 2019Assignee: Lattice Semiconductor CorporationInventors: Srirama Chandra, Robert Bartel
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Patent number: 9819174Abstract: Techniques are provided to control hotswap operations with programmable logic devices (PLDs). In particular, a MOSFET is provided to limit an in-rush current drawn from a power supply by capacitive components of an electronic assembly when it is plugged into the live, power supply. A controller with an algorithm is provided to control the MOSFET based on the in-rush current detected at the MOSFET. As such, a feedback control loop is established to selectively bias the gate of the MOSFET based on the detected in-rush current. The algorithm may limit the in-rush current based on a Safe Operating Area (SOA) of the MOSFET. The hotswap process may include multiple phases each with a voltage and/or current limit modeling the voltages and currents of the SOA. The algorithm may transition through the phases with the respective current and/or voltage limits during the hotswap process.Type: GrantFiled: January 29, 2015Date of Patent: November 14, 2017Assignee: Lattice Semiconductor CorporationInventors: Christopher W. Dix, Cleo Mui, Cheng-Jen Gwo, Joel Coplen, Srirama Chandra
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Patent number: 9772856Abstract: In one embodiment, a system has a master programmable device (PD) with native dual-boot capability and one or more slave PDs with no native dual-boot capability. A master golden image includes an embedded dual-boot function. During power-up, each PD copies its primary image into its volatile configuration memory and determines whether the primary image is valid. When the master's configuration engine detects an invalid master primary image, then the master's native dual-boot capability enables the master to implement a system-reboot procedure, which includes copying the master golden image from an external memory device into the master's volatile configuration memory and launching the embedded dual-boot function, which in turn copies the slave golden images from the external memory device into the slaves' volatile configuration memories before enabling other master-golden-image functions. Significant system reliability and robustness are achieved without provisioning every PD with native dual-boot capability.Type: GrantFiled: July 10, 2014Date of Patent: September 26, 2017Assignee: Lattice Semiconductor CorporationInventors: Srirama Chandra, Cleo Mui, Cheng Jen Gwo, Saurabh Chheda
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Publication number: 20170031885Abstract: An electronic device associated with rendering of web content, a server, and a controlling method thereof are provided. The controlling method includes receiving a request for the web content from an electronic device by the server executing a program for a content renderer, generating a render structure associated with render commands by the server executing the program for the content renderer, and sending, by the server executing the program for the content renderer, the render structure to the electronic device to render the web content, and the render commands are issued to each layer of a rendering engine to render the web content of the electronic device.Type: ApplicationFiled: July 29, 2016Publication date: February 2, 2017Inventors: Naveen Kumar S G, Pruthvi Kumar MADUGUNDU, Srirama Chandra Sekhar MOGALI, Joy BOSE
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Publication number: 20160226241Abstract: Techniques are provided to control hotswap operations with programmable logic devices (PLDs). In particular, a MOSFET is provided to limit an in-rush current drawn from a power supply by capacitive components of an electronic assembly when it is plugged into the live, power supply. A controller with an algorithm is provided to control the MOSFET based on the in-rush current detected at the MOSFET. As such, a feedback control loop is established to selectively bias the gate of the MOSFET based on the detected in-rush current. The algorithm may limit the in-rush current based on a Safe Operating Area (SOA) of the MOSFET. The hotswap process may include multiple phases each with a voltage and/or current limit modeling the voltages and currents of the SOA. The algorithm may transition through the phases with the respective current and/or voltage limits during the hotswap process.Type: ApplicationFiled: January 29, 2015Publication date: August 4, 2016Inventors: Christopher W. Dix, Cleo Mui, Cheng-Jen Gwo, Joel Coplen, Srirama Chandra