Abstract: In one embodiment, a reconfigurable and scalable hardware management architecture includes a digital controller for controlling two or more analog sense-and-control (ASC) circuits, where each ASC monitors voltage, current, and temperature of one or more power supplies (e.g., DC-to-DC converters), ICs, or a circuit board. The controller and ASCs are connected in a star architecture, where each ASC is connected to the controller via a different, dedicated interface to communicate regarding the power supplies being monitored. In addition, the controller and the ASCs are also connected in a bus architecture via a shared interface. The architecture can be re-configured by adding one or more additional ASCs or by removing one or more existing ASCs, where each additional ASC is (i) connected to a different I/O interface of the digital controller via a different, dedicated interface and (ii) connected to the digital controller and the two or more existing ASCs via the shared interface.

Abstract: In one embodiment, a system has a master programmable device (PD) with native dual-boot capability and one or more slave PDs with no native dual-boot capability. A master golden image includes an embedded dual-boot function. During power-up, each PD copies its primary image into its volatile configuration memory and determines whether the primary image is valid. When the master's configuration engine detects an invalid master primary image, then the master's native dual-boot capability enables the master to implement a system-reboot procedure, which includes copying the master golden image from an external memory device into the master's volatile configuration memory and launching the embedded dual-boot function, which in turn copies the slave golden images from the external memory device into the slaves' volatile configuration memories before enabling other master-golden-image functions. Significant system reliability and robustness are achieved without provisioning every PD with native dual-boot capability.

Abstract: The present invention provides nitrofurfuryl substituted phenyl linked piperidino-oxadiazolone compounds of general formula (A) as anti-tubercular agents; wherein G=formula (B); X?H, F; R?H, CH3, C2H5, Benzyl.

Abstract: The present invention provides nitrofurfuryl substituted phenyl linked piperidino-oxadiazolone compounds of general formula (A) as anti-tubercular agents; wherein G=formula (B); X?H, F; R?H, CH3, C2H5, Benzyl.

Abstract: The present invention provides a compound of general formula A, useful as potential anticancer agents against eleven human cancer cell lines. The present invention further provides a process for the preparation of diaryl ether linked pyrrolo[2,1-c][1,4]benzodi azepine conjugates attached through different alkane spacers of general formula A.

Abstract: The present invention provides a compound of general formula A, useful as potential antitumour agents against five human cancer cell lines. The present invention further provides a process for the preparation of pyrrolo[2,1-c][1,4]naphthodiazepine linked substituted piperazine conjugates attached through different alkane spacers of general formula A. (Formula I) General formula A. Where R=R?=(Formula II). n=1-9 and R?=methyl, ethyl, acetyl, benzyl, piperinoyl, 4-fluorophenyl, 4-chlorophenyl, 4-methoxyphenyl, pyridyl, pyrimidyl.

Abstract: The present invention provides a compound of general formula A, useful as potential anticancer agents against eleven human cancer cell lines. The present invention further provides a process for the preparation of diaryl ether linked pyrrolo[2,1-c][1,4]benzodiazepine conjugates attached through different alkane spacers of general formula A.

Abstract: The present invention provides a compound of general formula A, useful as potential antitumour agents against five human cancer cell lines. The present invention further provides a process for the preparation of pyrrolo[2,1-c][1,4]naphthodiazepine linked substituted piperazine conjugates attached through different alkane spacers of general formula A. (Formula I) General formula A. Where R=R?=(Formula II).

Abstract: A programming technique for a programmable logic device (PLD) is disclosed wherein the programmed PLD controls a circuit's behavior according to a desired circuit behavior implementation. A user constructs a program, wherein the program comprises instructions defining inputs, outputs, and conditional branching for an abstract state sequencer that implements the desired circuit behavior. The programming technique then translates the states and resources for the abstract state sequencer into HDL source code, which in turn may be translated into a programming bit pattern for the PLD.