Patents by Inventor Srivatsan Varadarajan
Srivatsan Varadarajan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230305887Abstract: Embodiments for improved processing efficiency between a processor and at least one coprocessor are disclosed. Some examples are directed to a processor-coprocessor scheduling in which workloads are scheduled to a coprocessor based on a timing window of the processor. In additional or alternative examples, workloads are assigned to the coprocessor based on the processing resources and/or an order of priority. In connection with the disclosed embodiments, the coprocessor can be implemented by a graphics processing unit (GPU), hardware processing accelerator, field-programmable gate array (FPGA), application-specific integrated circuit (ASIC), or other processing circuitry. The processor can be implemented by a central processing unit (CPU) or other processing circuitry.Type: ApplicationFiled: March 28, 2022Publication date: September 28, 2023Applicant: Honeywell International s.r.o.Inventors: Pavel Zaykov, Larry James Miller, Humberto Carvalho, Srivatsan Varadarajan
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Publication number: 20230305888Abstract: Embodiments for improved processing efficiency between a processor and at least one coprocessor are disclosed. Some examples are directed to mapping of workloads to one or more clusters of a coprocessor for execution based on a coprocessor assignment policy. In connection with the disclosed embodiments, the coprocessor can be implemented by a graphics processing unit (GPU), hardware processing accelerator, field-programmable gate array (FPGA), application-specific integrated circuit (ASIC), or other processing circuitry. The processor can be implemented by a central processing unit (CPU) or other processing circuitry.Type: ApplicationFiled: March 29, 2022Publication date: September 28, 2023Applicant: Honeywell International s.r.o.Inventors: Pavel Zaykov, Larry James Miller, Humberto Carvalho, Srivatsan Varadarajan
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Patent number: 11769257Abstract: In one embodiment, a vision aided navigation system comprises: at least one image sensor configured to produce image frames of a surrounding environment; a feature extractor configured to extract at least one image feature from a first image frame; a navigation filter configured to output a navigation solution based navigation data from a navigation device and changes in position of the image feature in the images; a feature tracker to receive the image frames and predict a location of the image feature in a subsequent image frame; a dynamic localized parameter adjuster to adjust at least one image parameter of the subsequent image frame; and wherein the feature tracker is configured so that when the image feature cannot be identified in the subsequent image frame within a bounded region around the predicted location, the dynamic localized parameter adjuster adjusts the at least one image parameter within the bounded region.Type: GrantFiled: May 30, 2019Date of Patent: September 26, 2023Assignee: Honeywell International Inc.Inventors: Benjamin Lee Johnson, Vibhor L Bageshwar, Srivatsan Varadarajan
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Publication number: 20230230256Abstract: In one embodiment, a vision aided navigation system comprises: at least one image sensor configured to produce image frames of a surrounding environment; a feature extractor configured to extract at least one image feature from a first image frame; a navigation filter configured to output a navigation solution based navigation data from a navigation device and changes in position of the image feature in the images; a feature tracker to receive the image frames and predict a location of the image feature in a subsequent image frame; a dynamic localized parameter adjuster to adjust at least one image parameter of the subsequent image frame; and wherein the feature tracker is configured so that when the image feature cannot be identified in the subsequent image frame within a bounded region around the predicted location, the dynamic localized parameter adjuster adjusts the at least one image parameter within the bounded region.Type: ApplicationFiled: May 30, 2019Publication date: July 20, 2023Applicant: Honeywell International Inc.Inventors: Benjamin Lee Johnson, Vibhor L Bageshwar, Srivatsan Varadarajan
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Patent number: 11552857Abstract: Methods, systems and apparatuses to enable an optimum bin selection by implementing a neural network with a network scheduling and configuration tool (NST), the method includes: configuring an agent with a critic function from neural networks wherein the agent neural network represents each bin of the collection of bins in the network that performs an action, and a critic function evaluates a criteria of success for performing the action; processing, by a scheduling algorithm, the VLs by the NST; determining one or more reward functions using global quality measurements based on criteria comprising: a lack of available bins, a lack of available VLs, and successfully scheduling operations of a VL into a bin; and training the network based on a normalized state model of the scheduled network by using input data sets to arrive at an optimum bin selection.Type: GrantFiled: August 28, 2019Date of Patent: January 10, 2023Assignee: HONEYWELL INTERNATIONAL INC.Inventors: Benjamin F. DeLay, Srivatsan Varadarajan
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Patent number: 11507420Abstract: Systems and methods for scheduling tasks using sliding time windows are provided. In certain embodiments, a system for scheduling the execution of tasks includes at least one processing unit configured to execute multiple tasks, wherein each task in the multiple tasks is scheduled to execute within a scheduler instance in multiple scheduler instances, each scheduler instance in the multiple scheduler instances being associated with a set of time windows in multiple time windows and with a set of processing units in the at least one processing unit in each time window, time windows in the plurality of time windows having a start time and an allotted duration and the scheduler instance associated with the time windows begins executing associated tasks no earlier than the start time and executes for no longer than the allotted duration, and wherein the start time is slidable to earlier moments in time.Type: GrantFiled: September 8, 2020Date of Patent: November 22, 2022Assignee: Honeywell International Inc.Inventors: Srivatsan Varadarajan, Larry James Miller, Arthur Kirk McCready, Aaron R. Larson, Richard Frost, Ryan Lawrence Roffelsen
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Patent number: 11409643Abstract: Techniques for determining worst-case execution time for at least one application under test are disclosed using memory thrashing. Memory thrashing simulates shared resource interference. Memory that is thrashed includes mapped memory, and optionally shared cache memory.Type: GrantFiled: February 19, 2020Date of Patent: August 9, 2022Assignee: Honeywell International IncInventors: Pavel Zaykov, Larry James Miller, Srivatsan Varadarajan
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Patent number: 11138043Abstract: Systems and methods for outlier mitigation in safety-critical systems are provided. In one embodiment, a computer system comprises: a processor comprising one or more processing cores; a scheduling function that schedules the execution of applications, the applications each comprise threads; a contingency budgeting manager (CBM) that defines at least a first pre-determined set of threads from the threads of the applications and assigns a contingency budget pool to the first set of threads. The first set of threads are each scheduled by the scheduling function to execute on a first processing core. The CBM is further configured to monitor execution of each of the threads of the first set of threads to identify when a first thread is an execution time outlier. When the CBM determines that the first thread is an execution time outlier, it allocates additional thread execution time from the contingency budget pool to the first thread.Type: GrantFiled: May 23, 2019Date of Patent: October 5, 2021Assignee: Honeywell International s.r.oInventors: Pavel Zaykov, Larry James Miller, Srivatsan Varadarajan, Chittaranjan Kashiwar
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Publication number: 20210133088Abstract: Techniques for determining worst-case execution time for at least one application under test are disclosed using memory thrashing. Memory thrashing simulates shared resource interference. Memory that is thrashed includes mapped memory, and optionally shared cache memory.Type: ApplicationFiled: February 19, 2020Publication date: May 6, 2021Applicant: Honeywell International Inc.Inventors: Pavel Zaykov, Larry James Miller, Srivatsan Varadarajan
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Publication number: 20210067417Abstract: Methods, systems and apparatuses to enable an optimum bin selection by implementing a neural network with a network scheduling and configuration tool (NST), the method includes: configuring an agent with a critic function from neural networks wherein the agent neural network represents each bin of the collection of bins in the network that performs an action, and a critic function evaluates a criteria of success for performing the action; processing, by a scheduling algorithm, the VLs by the NST; determining one or more reward functions using global quality measurements based on criteria comprising: a lack of available bins, a lack of available VLs, and successfully scheduling operations of a VL into a bin; and training the network based on a normalized state model of the scheduled network by using input data sets to arrive at an optimum bin selection.Type: ApplicationFiled: August 28, 2019Publication date: March 4, 2021Applicant: HONEYWELL INTERNATIONAL INC.Inventors: Benjamin F. DeLay, Srivatsan Varadarajan
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Publication number: 20210067459Abstract: Methods, systems and apparatuses for scheduling a plurality of Virtual Links (VLs) in a Time-Triggered Ethernet (TTE) network by a network scheduling and configuration tool (NST) by establishing a collection of bins that corresponds to the smallest harmonic period allowing full network traversal of a time-triggered traffic packet in the network for determining available bin sets for sending the VL data by the NST; processing by a scheduling algorithm the VLs to be sent in accordance with a strict order comprising scheduling all the highest rate VLs prior to scheduling lower rate VLs; and scheduling reservations for the VLs in bins by tracking the available time available in each bin and optionally spreading the VL data across available bin sets by sorting a list of available bins by ascending bin utilization and by specifying a left-to-right or right-to-left sort order when searching for available bins based on a position in the timeline between the transmitter and receiver end stations.Type: ApplicationFiled: August 28, 2019Publication date: March 4, 2021Applicant: HONEYWELL INTERNATIONAL INC.Inventors: Benjamin F. DeLay, Srivatsan Varadarajan, Theodore J. Bonk, William T. Smithgall, Brent A. Morin
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Patent number: 10917355Abstract: Methods, systems and apparatuses for scheduling a plurality of Virtual Links (VLs) in a Time-Triggered Ethernet (TTE) network by a network scheduling and configuration tool (NST) by establishing a collection of bins that corresponds to the smallest harmonic period allowing full network traversal of a time-triggered traffic packet in the network for determining available bin sets for sending the VL data by the NST; processing by a scheduling algorithm the VLs to be sent in accordance with a strict order comprising scheduling all the highest rate VLs prior to scheduling lower rate VLs; and scheduling reservations for the VLs in bins by tracking the available time available in each bin and optionally spreading the VL data across available bin sets by sorting a list of available bins by ascending bin utilization and by specifying a left-to-right or right-to-left sort order when searching for available bins based on a position in the timeline between the transmitter and receiver end stations.Type: GrantFiled: August 28, 2019Date of Patent: February 9, 2021Assignee: HONEYWELL INTERNATIONAL INC.Inventors: Benjamin F. DeLay, Srivatsan Varadarajan, Theodore J. Bonk, William T. Smithgall, Brent A. Morin
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Patent number: 10908955Abstract: A method is provided. The method comprises: commencing a time window, where the time window has a fixed or variable time duration; determining a shared resource access quota for at least one time partition for the time window, where the shared resource access quota may vary by time window; allocating each determined shared resource access quota to a corresponding time partition for the window; determining if allocated shared resource access quota for any time partition in the time window has been met or exceeded; and if an allocated shared resource access quota for a time partition in the time window has been met or exceeded, then halting an executing process in the time partition.Type: GrantFiled: March 22, 2018Date of Patent: February 2, 2021Assignee: Honeywell International Inc.Inventors: Srivatsan Varadarajan, Larry James Miller, Chittaranjan Kashiwar, Pavel Zaykov
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Patent number: 10887244Abstract: Methods, systems and apparatuses for scheduling a plurality of Virtual Links (VLs) in a Time-Triggered Ethernet (TTE) network by determining a weight for each of the plurality of VLs, the determined weight being proportional to a demand each of the plurality of VLs will place on the time-triggered ethernet network; generating a plurality of bins whose length in time is harmonic to all the scheduled rates of the plurality of VLs; determining a demand value proportional to how often the bin is expected to be used based upon a green zone of each of the plurality of VLs and the determined weight for each of the plurality of VLs; updating the demand value for each bin within the green zone; sorting the plurality of bins from least demanded to most demanded based upon the updated demand value; and scheduling the sorted plurality of VLs within the sorted plurality of bins.Type: GrantFiled: August 28, 2019Date of Patent: January 5, 2021Assignee: HONEYWELL INTERNATIONAL INC.Inventors: Benjamin F. DeLay, Srivatsan Varadarajan
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Publication number: 20200401450Abstract: Systems and methods for scheduling tasks using sliding time windows are provided. In certain embodiments, a system for scheduling the execution of tasks includes at least one processing unit configured to execute multiple tasks, wherein each task in the multiple tasks is scheduled to execute within a scheduler instance in multiple scheduler instances, each scheduler instance in the multiple scheduler instances being associated with a set of time windows in multiple time windows and with a set of processing units in the at least one processing unit in each time window, time windows in the plurality of time windows having a start time and an allotted duration and the scheduler instance associated with the time windows begins executing associated tasks no earlier than the start time and executes for no longer than the allotted duration, and wherein the start time is slidable to earlier moments in time.Type: ApplicationFiled: September 8, 2020Publication date: December 24, 2020Applicant: Honeywell International Inc.Inventors: Srivatsan Varadarajan, Larry James Miller, Arthur Kirk McCready, Aaron R. Larson, Richard Frost, Ryan Lawrence Roffelsen
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Publication number: 20200371840Abstract: Systems and methods for outlier mitigation in safety-critical systems are provided. In one embodiment, a computer system comprises: a processor comprising one or more processing cores; a scheduling function that schedules the execution of applications, the applications each comprise threads; a contingency budgeting manager (CBM) that defines at least a first pre-determined set of threads from the threads of the applications and assigns a contingency budget pool to the first set of threads. The first set of threads are each scheduled by the scheduling function to execute on a first processing core. The CBM is further configured to monitor execution of each of the threads of the first set of threads to identify when a first thread is an execution time outlier. When the CBM determines that the first thread is an execution time outlier, it allocates additional thread execution time from the contingency budget pool to the first thread.Type: ApplicationFiled: May 23, 2019Publication date: November 26, 2020Applicant: Honeywell International s.r.o.Inventors: Pavel Zaykov, Larry James Miller, Srivatsan Varadarajan, Chittaranjan Kashiwar
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Patent number: 10768984Abstract: Systems and methods for scheduling tasks using sliding time windows are provided. In certain embodiments, a system for scheduling the execution of tasks includes at least one processing unit configured to execute multiple tasks, wherein each task in the multiple tasks is scheduled to execute within a scheduler instance in multiple scheduler instances, each scheduler instance in the multiple scheduler instances being associated with a set of time windows in multiple time windows and with a set of processing units in the at least one processing unit in each time window, time windows in the plurality of time windows having a start time and an allotted duration and the scheduler instance associated with the time windows begins executing associated tasks no earlier than the start time and executes for no longer than the allotted duration, and wherein the start time is slidable to earlier moments in time.Type: GrantFiled: June 11, 2015Date of Patent: September 8, 2020Assignee: Honeywell International Inc.Inventors: Srivatsan Varadarajan, Larry James Miller, Arthur Kirk McCready, Aaron R. Larson, Richard Frost, Ryan Lawrence Roffelsen
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Publication number: 20190294472Abstract: A method is provided. The method comprises: commencing a time window, where the time window has a fixed or variable time duration; determining a shared resource access quota for at least one time partition for the time window, where the shared resource access quota may vary by time window; allocating each determined shared resource access quota to a corresponding time partition for the window; determining if allocated shared resource access quota for any time partition in the time window has been met or exceeded; and if an allocated shared resource access quota for a time partition in the time window has been met or exceeded, then halting an executing process in the time partition.Type: ApplicationFiled: March 22, 2018Publication date: September 26, 2019Applicant: Honeywell International Inc.Inventors: Srivatsan Varadarajan, Larry James Miller, Chittaranjan Kashiwar, Pavel Zaykov
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Patent number: 9769082Abstract: Systems and methods for network bandwidth, buffers and timing management using hybrid scheduling of traffic with different priorities and guarantees are provided. In certain embodiments, a method of managing network scheduling and configuration comprises, for each transmitting end station, reserving one exclusive buffer for each virtual link to be transmitted from the transmitting end station; for each receiving end station, reserving exclusive buffers for each virtual link to be received at the receiving end station; and for each switch, reserving a exclusive buffer for each virtual link to be received at an input port of the switch. The method further comprises determining if each respective transmitting end station, receiving end station, and switch has sufficient capability to support the reserved buffers; and reporting buffer infeasibility if each respective transmitting end station, receiving end station, and switch does not have sufficient capability to support the reserved buffers.Type: GrantFiled: April 1, 2015Date of Patent: September 19, 2017Assignee: Honeywell International Inc.Inventors: Srivatsan Varadarajan, Brendan Hall, William Todd Smithgall, Ted Bonk, Benjamin F. DeLay
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Patent number: 9769075Abstract: Systems and methods for interference cognizant network scheduling are provided. In certain embodiments, a method of scheduling communications in a network comprises identifying a bin of a global timeline for scheduling an unscheduled virtual link, wherein a bin is a segment of the timeline; identifying a pre-scheduled virtual link in the bin; and determining if the pre-scheduled and unscheduled virtual links share a port. In certain embodiments, if the unscheduled and pre-scheduled virtual links don't share a port, scheduling transmission of the unscheduled virtual link to overlap with the scheduled transmission of the pre-scheduled virtual link; and if the unscheduled and pre-scheduled virtual links share a port: determining a start time delay for the unscheduled virtual link based on the port; and scheduling transmission of the unscheduled virtual link in the bin based on the start time delay to overlap part of the scheduled transmission of the pre-scheduled virtual link.Type: GrantFiled: April 1, 2015Date of Patent: September 19, 2017Assignee: Honeywell International Inc.Inventors: Srivatsan Varadarajan, Brendan Hall, William Todd Smithgall, Ted Bonk, Benjamin F. DeLay