Patents by Inventor Srivatsan Varadarajan

Srivatsan Varadarajan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9762501
    Abstract: Systems and methods for systematic hybrid network scheduling for multiple traffic classes with host timing and phase constraints are provided. In certain embodiments, a method of scheduling communications in a network comprises scheduling transmission of virtual links pertaining to a first traffic class on a global schedule to coordinate transmission of the virtual links pertaining to the first traffic class across all transmitting end stations on the global schedule; and scheduling transmission of each virtual link pertaining to a second traffic class on a local schedule of the respective transmitting end station from which each respective virtual link pertaining to the second traffic class is transmitted such that transmission of each virtual link pertaining to the second traffic class is coordinated only at the respective end station from which each respective virtual link pertaining to the second traffic class is transmitted.
    Type: Grant
    Filed: April 1, 2015
    Date of Patent: September 12, 2017
    Assignee: Honeywell International Inc.
    Inventors: Srivatsan Varadarajan, Brendan Hall, William Todd Smithgall, Ted Bonk, Benjamin F. DeLay
  • Patent number: 9612868
    Abstract: Systems and methods for instruction entity allocation and scheduling on multi-processors is provided. In at least one embodiment, a method for generating an execution schedule for a plurality of instruction entities for execution on a plurality of processing units comprises arranging the plurality of instruction entities into a sorted order and allocating instruction entities in the plurality of instruction entities to individual processing units in the plurality of processing units. The method further comprises scheduling instances of the instruction entities in scheduled time windows in the execution schedule, wherein the instances of the instruction entities are scheduled in scheduled time windows according to the sorted order of the plurality of instruction entities and organizing the execution schedule into execution groups.
    Type: Grant
    Filed: October 31, 2012
    Date of Patent: April 4, 2017
    Assignee: Honeywell International Inc.
    Inventors: Arvind Easwaran, Srivatsan Varadarajan
  • Publication number: 20170006047
    Abstract: Methods and systems are provided for monitoring cyber activity in a system having multiple networks. A method includes: receiving an evidence stream generated by a plurality of monitoring systems associated with a plurality of hardware and software components that communicate over the multiple networks; processing the evidence stream using at least one reference model to identify at least one cyber issue, where the cyber issue relates to at least one of security, safety, and resources; and generating at least one of actuator data and user interface data based on the identified cyber issue.
    Type: Application
    Filed: June 30, 2015
    Publication date: January 5, 2017
    Applicant: HONEYWELL INTERNATIONAL INC.
    Inventors: Raj Mohan Bharadwaj, Srivatsan Varadarajan, Darryl Busch, Jun Ho Huh, Daniel P. Johnson
  • Publication number: 20160364267
    Abstract: Systems and methods for scheduling tasks using sliding time windows are provided. In certain embodiments, a system for scheduling the execution of tasks includes at least one processing unit configured to execute multiple tasks, wherein each task in the multiple tasks is scheduled to execute within a scheduler instance in multiple scheduler instances, each scheduler instance in the multiple scheduler instances being associated with a set of time windows in multiple time windows and with a set of processing units in the at least one processing unit in each time window, time windows in the plurality of time windows having a start time and an allotted duration and the scheduler instance associated with the time windows begins executing associated tasks no earlier than the start time and executes for no longer than the allotted duration, and wherein the start time is slidable to earlier moments in time.
    Type: Application
    Filed: June 11, 2015
    Publication date: December 15, 2016
    Inventors: Srivatsan Varadarajan, Larry James Miller, Arthur Kirk McCready, Aaron R. Larson, Richard Frost, Ryan Lawrence Roffelsen
  • Publication number: 20160294720
    Abstract: Systems and methods for systematic hybrid network scheduling for multiple traffic classes with host timing and phase constraints are provided. In certain embodiments, a method of scheduling communications in a network comprises scheduling transmission of virtual links pertaining to a first traffic class on a global schedule to coordinate transmission of the virtual links pertaining to the first traffic class across all transmitting end stations on the global schedule; and scheduling transmission of each virtual link pertaining to a second traffic class on a local schedule of the respective transmitting end station from which each respective virtual link pertaining to the second traffic class is transmitted such that transmission of each virtual link pertaining to the second traffic class is coordinated only at the respective end station from which each respective virtual link pertaining to the second traffic class is transmitted.
    Type: Application
    Filed: April 1, 2015
    Publication date: October 6, 2016
    Inventors: Srivatsan Varadarajan, Brendan Hall, William Todd Smithgall, Ted Bonk, Benjamin F. DeLay
  • Publication number: 20160294697
    Abstract: Systems and methods for interference cognizant network scheduling are provided. In certain embodiments, a method of scheduling communications in a network comprises identifying a bin of a global timeline for scheduling an unscheduled virtual link, wherein a bin is a segment of the timeline; identifying a pre-scheduled virtual link in the bin; and determining if the pre-scheduled and unscheduled virtual links share a port. In certain embodiments, if the unscheduled and pre-scheduled virtual links don't share a port, scheduling transmission of the unscheduled virtual link to overlap with the scheduled transmission of the pre-scheduled virtual link; and if the unscheduled and pre-scheduled virtual links share a port: determining a start time delay for the unscheduled virtual link based on the port; and scheduling transmission of the unscheduled virtual link in the bin based on the start time delay to overlap part of the scheduled transmission of the pre-scheduled virtual link.
    Type: Application
    Filed: April 1, 2015
    Publication date: October 6, 2016
    Inventors: Srivatsan Varadarajan, Brendan Hall, William Todd Smithgall, Ted Bonk, Benjamin F. DeLay
  • Publication number: 20160294721
    Abstract: Systems and methods for network bandwidth, buffers and timing management using hybrid scheduling of traffic with different priorities and guarantees are provided. In certain embodiments, a method of managing network scheduling and configuration comprises, for each transmitting end station, reserving one exclusive buffer for each virtual link to be transmitted from the transmitting end station; for each receiving end station, reserving exclusive buffers for each virtual link to be received at the receiving end station; and for each switch, reserving a exclusive buffer for each virtual link to be received at an input port of the switch. The method further comprises determining if each respective transmitting end station, receiving end station, and switch has sufficient capability to support the reserved buffers; and reporting buffer infeasibility if each respective transmitting end station, receiving end station, and switch does not have sufficient capability to support the reserved buffers.
    Type: Application
    Filed: April 1, 2015
    Publication date: October 6, 2016
    Inventors: Srivatsan Varadarajan, Brendan Hall, William Todd Smithgall, Ted Bonk, Benjamin F. DeLay
  • Publication number: 20160249231
    Abstract: A method for optimizing a wireless network comprises obtaining local measurement and feedback data from a single node in the network; estimating a state of the node by using the local measurement and feedback data in an analysis framework model of the wireless network; applying the estimated state of the node to a local control law to determine one or more local protocol parameter updates for the node; and transmitting the one or more local protocol parameter updates to the node in the network.
    Type: Application
    Filed: February 23, 2015
    Publication date: August 25, 2016
    Inventors: Kartik B. Ariyur, Srivatsan Varadarajan, Yunjung Yi
  • Patent number: 9306766
    Abstract: A communication switch comprises a plurality of ports and a processing unit configured to identify source ports and destination ports from the plurality of ports on a per virtual link basis. Each virtual link comprises one or more source ports via which frames are received from one or more source nodes and one or more destination ports via which received frames are forwarded to one or more destination nodes. For at least one virtual link, the processing unit is configured to accept more than one of the plurality of ports as source ports.
    Type: Grant
    Filed: March 28, 2011
    Date of Patent: April 5, 2016
    Assignee: Honeywell International Inc.
    Inventors: Brendan Hall, Srivatsan Varadarajan, Guenther Bauer, Wilfried Steiner
  • Patent number: 8976790
    Abstract: A method comprises transmitting a plurality of copies of a message from each of a first transmission node and a second transmission node, each copy having a respective identification and forwarding each of the plurality of copies of the message among other nodes in the network based, at least in part, on the respective identification of each copy such that each copy of the message traverses a predetermined communication path among the other nodes. A respective first received copy is compared to a respective second received copy at each of the other nodes. The integrity of the respective first and second copies is validated at each of the other nodes if the copies match and the copies traversed disjoint communication paths.
    Type: Grant
    Filed: August 3, 2012
    Date of Patent: March 10, 2015
    Assignee: Honeywell International Inc.
    Inventors: Brendan Hall, Kevin R. Driscoll, Srivatsan Varadarajan
  • Patent number: 8908675
    Abstract: A network comprises a plurality of nodes; and a plurality of links communicatively coupling each of the plurality of nodes to at least one respective adjacent node of the plurality of nodes via a first communication channel and to another respective adjacent node of the plurality of nodes via a second communication channel. At least one of the plurality of nodes is a source node configured to source data. The source node is configured to form a virtual self-checking pair with one of the respective adjacent node on the first communication channel or the respective adjacent node on the second communication channel to achieve a consistent broadcast of data on the first and second communication channels. Data exchanged between the source node and the respective adjacent node in the virtual self-checking pair is only sourced by the source node.
    Type: Grant
    Filed: January 13, 2012
    Date of Patent: December 9, 2014
    Assignee: Honeywell International Inc.
    Inventors: Brendan Hall, Srivatsan Varadarajan, Kevin R. Driscoll
  • Publication number: 20140122848
    Abstract: Systems and methods for instruction entity allocation and scheduling on multi-processors is provided. In at least one embodiment, a method for generating an execution schedule for a plurality of instruction entities for execution on a plurality of processing units comprises arranging the plurality of instruction entities into a sorted order and allocating instruction entities in the plurality of instruction entities to individual processing units in the plurality of processing units. The method further comprises scheduling instances of the instruction entities in scheduled time windows in the execution schedule, wherein the instances of the instruction entities are scheduled in scheduled time windows according to the sorted order of the plurality of instruction entities and organizing the execution schedule into execution groups.
    Type: Application
    Filed: October 31, 2012
    Publication date: May 1, 2014
    Applicant: HONEYWELL INTERNATIONAL INC.
    Inventors: Arvind Easwaran, Srivatsan Varadarajan
  • Patent number: 8665884
    Abstract: A system comprises a plurality of nodes, at least one of the plurality of nodes configured to insert, on a per-virtual link basis, a delay value into a dynamic delay field of a frame corresponding to the respective virtual link, wherein the dynamic delay value represents latency of frames of the respective virtual link. The system also comprises a switch having a plurality of ports, each port coupled to one of the plurality of nodes. The switch is configured to route frames received from the plurality of nodes to one or more of the plurality of nodes. At least one of the plurality of nodes is configured to store frames received from the switch in a buffer and to update the value in the dynamic delay field to reflect the end-to-end system delay.
    Type: Grant
    Filed: August 25, 2011
    Date of Patent: March 4, 2014
    Assignees: Honeywell International Inc., TTTech Computertechnik AG
    Inventors: Brendan Hall, Srivatsan Varadarajan, Wilfried Steiner, Guenther Bauer
  • Publication number: 20140036735
    Abstract: A method comprises transmitting a plurality of copies of a message from each of a first transmission node and a second transmission node, each copy having a respective identification and forwarding each of the plurality of copies of the message among other nodes in the network based, at least in part, on the respective identification of each copy such that each copy of the message traverses a predetermined communication path among the other nodes. A respective first received copy is compared to a respective second received copy at each of the other nodes. The integrity of the respective first and second copies is validated at each of the other nodes if the copies match and the copies traversed disjoint communication paths.
    Type: Application
    Filed: August 3, 2012
    Publication date: February 6, 2014
    Applicant: HONEYWELL INTERNATIONAL INC.
    Inventors: Brendan Hall, Kevin R. Driscoll, Srivatsan Varadarajan
  • Patent number: 8634305
    Abstract: Methods and apparatus are provided for evaluating the performance of a Time Triggered Ethernet (TTE) system employing Time Triggered (TT) communication. A real TTE system under test (SUT) having real input elements communicating using TT messages with output elements via one or more first TTE switches during a first time interval schedule established for the SUT. A simulation system is also provided having input simulators that communicate using TT messages via one or more second TTE switches with the same output elements during a second time interval schedule established for the simulation system. The first and second time interval schedules are off-set slightly so that messages from the input simulators, when present, arrive at the output elements prior to messages from the analogous real inputs, thereby having priority over messages from the real inputs and causing the system to operate based on the simulated inputs when present.
    Type: Grant
    Filed: September 2, 2011
    Date of Patent: January 21, 2014
    Assignee: Honeywell International Inc.
    Inventors: William Todd Smithgall, Brendan Hall, Srivatsan Varadarajan
  • Publication number: 20130182552
    Abstract: A network comprises a plurality of nodes; and a plurality of links communicatively coupling each of the plurality of nodes to at least one respective adjacent node of the plurality of nodes via a first communication channel and to another respective adjacent node of the plurality of nodes via a second communication channel. At least one of the plurality of nodes is a source node configured to source data. The source node is configured to form a virtual self-checking pair with one of the respective adjacent node on the first communication channel or the respective adjacent node on the second communication channel to achieve a consistent broadcast of data on the first and second communication channels. Data exchanged between the source node and the respective adjacent node in the virtual self-checking pair is only sourced by the source node.
    Type: Application
    Filed: January 13, 2012
    Publication date: July 18, 2013
    Applicant: HONEYWELL INTERNATIONAL INC.
    Inventors: Brendan Hall, Srivatsan Varadarajan, Kevin R. Driscoll
  • Patent number: 8448002
    Abstract: A clock module is coupled in parallel to a number of data processing modules that are coupled in series. The data processing modules can be individually clock-gated. Each of the data processing modules can determine whether or not it can be placed into an idle state. To reduce power consumption, any subset of the data processing modules that are eligible to be placed in an idle state can be clock-gated. The remaining data processing modules can continue to receive clock signals from the clock module and thus can continue to process data.
    Type: Grant
    Filed: April 10, 2008
    Date of Patent: May 21, 2013
    Assignee: Nvidia Corporation
    Inventors: Ravi Bulusu, Shu-Jen Fang, Srivatsan Varadarajan, Han Chou, Sandro Pintz, Aiyun Wang
  • Publication number: 20130058217
    Abstract: Methods and apparatus are provided for evaluating the performance of a Time Triggered Ethernet (TTE) system employing Time Triggered (TT) communication. A real TTE system under test (SUT) having real input elements communicating using TT messages with output elements via one or more first TTE switches during a first time interval schedule established for the SUT. A simulation system is also provided having input simulators that communicate using TT messages via one or more second TTE switches with the same output elements during a second time interval schedule established for the simulation system. The first and second time interval schedules are off-set slightly so that messages from the input simulators, when present, arrive at the output elements prior to messages from the analogous real inputs, thereby having priority over messages from the real inputs and causing the system to operate based on the simulated inputs when present.
    Type: Application
    Filed: September 2, 2011
    Publication date: March 7, 2013
    Applicant: HONEYWELL INTERNATIONAL INC.
    Inventors: William Todd Smithgall, Brendan Hall, Srivatsan Varadarajan
  • Publication number: 20130051396
    Abstract: A system comprises a plurality of nodes, at least one of the plurality of nodes configured to insert, on a per-virtual link basis, a delay value into a dynamic delay field of a frame corresponding to the respective virtual link, wherein the dynamic delay value represents latency of frames of the respective virtual link. The system also comprises a switch having a plurality of ports, each port coupled to one of the plurality of nodes. The switch is configured to route frames received from the plurality of nodes to one or more of the plurality of nodes. At least one of the plurality of nodes is configured to store frames received from the switch in a buffer and to update the value in the dynamic delay field to reflect the end-to-end system delay.
    Type: Application
    Filed: August 25, 2011
    Publication date: February 28, 2013
    Applicants: TTTECH COMPUTERTECHNIK AG, HONEYWELL INTERNATIONAL INC.
    Inventors: Brendan Hall, Srivatsan Varadarajan, Wilfried Steiner, Guenther Bauer
  • Publication number: 20120250572
    Abstract: A communication switch comprises a plurality of ports and a processing unit configured to identify source ports and destination ports from the plurality of ports on a per virtual link basis. Each virtual link comprises one or more source ports via which frames are received from one or more source nodes and one or more destination ports via which received frames are forwarded to one or more destination nodes. For at least one virtual link, the processing unit is configured to accept more than one of the plurality of ports as source ports.
    Type: Application
    Filed: March 28, 2011
    Publication date: October 4, 2012
    Applicants: TTTECH COMPUTERTECHNIK AG, HONEYWELL INTERNATIONAL INC.
    Inventors: Brendan Hall, Srivatsan Varadarajan, Guenther Bauer, Wilfried Steiner