Patents by Inventor Stéphane Bouvier

Stéphane Bouvier has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240006404
    Abstract: RC-network components that include a substrate and capacitor having a thin-film top electrode portion at a surface on one side of the substrate. The low ohmic semiconductor substrate is doped to contribute 5% or less to the resistance of the RC-network component. The resistance provided in series with the capacitor is controlled by providing a contact plate, spaced from the thin-film top electrode portion by an insulating layer, and a set of one or more bridging contacts passing through openings in the insulating layer. The bridging contacts electrically interconnect the thin-film top electrode portion and the contact plate. Different resistance values can be set by appropriate selection of the number of bridging contacts. The openings are elongated thereby reducing temperature concentration at their periphery. Correspondingly, the bridging contacts have an elongated cross-sectional shape.
    Type: Application
    Filed: September 15, 2022
    Publication date: January 4, 2024
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Yohei YAMAGUCHI, Yasuhiro MURASE, Stéphane BOUVIER
  • Publication number: 20230125974
    Abstract: A semi-conductor structure with selective bottom terminal contacting is described. The semiconductor device comprises a first metal layer disposed over a substrate; a conductive layer disposed over the first metal layer; and a second metal layer disposed over the conductive layer, the second metal layer embedding a porous structure comprising a plurality of pores that extend substantially perpendicularly from a top surface of the porous structure toward the conductive layer, wherein only a subset of the plurality of pores open onto the conductive layer.
    Type: Application
    Filed: December 23, 2022
    Publication date: April 27, 2023
    Inventors: Julien EL SABAHY, Larry BUFFLE, Stéphane BOUVIER, Frédéric VOIRON
  • Publication number: 20230012912
    Abstract: An electronic device is provided that includes a board equipped with a pair of differential transmission lines that each have an opening extending between two line terminals. Moreover, the device includes a capacitor module that includes a support and two capacitors that each have two capacitor terminals, respectively, connected to the two line terminals of one line of the pair of transmission lines. In addition, the support includes a separating region between the two capacitors that has at least one cavity disposed between the two capacitors.
    Type: Application
    Filed: September 16, 2022
    Publication date: January 19, 2023
    Inventors: Stéphane BOUVIER, David DENIS, Emmanuel LEFEUVRE
  • Publication number: 20230017133
    Abstract: RC-network components that include a substrate having a capacitor with a thin-film top electrode portion at a surface at one side of the substrate. The low ohmic semiconductor substrate is doped to contribute 5% or less to the resistance of the RC-network component. The resistance in series with the capacitor is controlled by providing a contact plate, spaced from the top electrode portion by an insulating layer, and a set of one or more bridging contacts in openings in the insulating layer. The bridging contacts electrically interconnect the top electrode portion and contact plate. Different resistance values can be set by appropriate selection of the number of bridging contacts. Temperature concentration at the periphery of the openings is reduced by providing reduced thickness portions in the insulating layer around the periphery of the openings.
    Type: Application
    Filed: September 26, 2022
    Publication date: January 19, 2023
    Inventors: Yohei YAMAGUCHI, Yasuhiro MURASE, Stéphane BOUVIER
  • Publication number: 20230010467
    Abstract: RC-network components that include a substrate and capacitor having a thin-film top electrode portion at a surface on one side of the substrate. The low ohmic semiconductor substrate is doped to contribute 5% or less to the resistance of the RC-network component. The resistance provided in series with the capacitor is controlled by providing a contact plate, spaced from the thin-film top electrode portion by an insulating layer, and a set of one or more bridging contacts passing through openings in the insulating layer. The bridging contacts electrically interconnect the thin-film top electrode portion and the contact plate. Different resistance values can be set by appropriate selection of the number of bridging contacts. The openings are elongated thereby reducing temperature concentration at their periphery. Correspondingly, the bridging contacts have an elongated cross-sectional shape.
    Type: Application
    Filed: September 15, 2022
    Publication date: January 12, 2023
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Yohei YAMAGUCHI, Yasuhiro MURASE, Stéphane BOUVIER
  • Publication number: 20220344100
    Abstract: An electronic device and a method for manufacturing an electronic device. The electronic device includes: a board equipped with a pair of differential transmission lines, each line of the pair having an opening extending between two line terminals; and a capacitor module that includes: a base; and two 3D capacitors supported by the base, each 3D capacitor comprising two capacitor terminals respectively connected to the two line terminals of one line of the pair of transmission lines.
    Type: Application
    Filed: July 8, 2022
    Publication date: October 27, 2022
    Inventors: Stéphane BOUVIER, David DENIS, Emmanuel LEFEUVRE
  • Publication number: 20220338349
    Abstract: A current path is provided through an interposer to ground a grounding pattern associated with a transmission line, by exploiting an interposer substrate that has a high-resistivity portion at a first surface and a low-resistivity portion extending from the high-resistivity portion to a second surface of the interposer. Moreover, a set of blind via-holes comprising electrically-conductive material extend from the first surface of the interposer substrate through the high-resistivity portion and into the low-resistivity portion. Top-to-bottom connection can be made using the conductive material in the blind vias and using the low-resistivity portion of the substrate, while the high-resistivity portion of the substrate impedes current leakage from the transmission line to the second surface of the substrate. The number and dimensions of the blind via-holes control the impedance of the grounding pattern relative to the transmission line's characteristic impedance.
    Type: Application
    Filed: June 27, 2022
    Publication date: October 20, 2022
    Inventors: Stéphane BOUVIER, Emmanuel LEFEUVRE, Frédéric VOIRON
  • Patent number: 11395632
    Abstract: The invention concerns an implementable semiconductor device that includes an electrode configured to be in contact with biological tissue and at least one capacitor, and wherein the capacitor includes a capacitor electrode having a first surface facing and in contact with the electrode configured to be in contact with biological tissue.
    Type: Grant
    Filed: October 3, 2019
    Date of Patent: July 26, 2022
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Nicolas Normand, Stéphane Bouvier
  • Publication number: 20220216350
    Abstract: A three-dimensional capacitor component that includes a substrate having a textured (contoured) surface and a stack of layers formed conformally over the textured surface to constitute a capacitive stack structure. Respective contacts to the bottom and top electrodes of the capacitive stack structure are both provided at a first side of the component. The bottom electrode and substrate are doped with dopants of the same polarity, and the substrate is heavily doped so that current between a terminal portion of the bottom electrode and remote parts of the bottom electrode flows via the substrate, lowering ESR. A backside metallization layer produces a further, and greater, reduction in ESR. The capacitor component may be implemented as a discrete capacitor component, but may also be integrated with other components/devices. Corresponding fabrication methods are described.
    Type: Application
    Filed: March 25, 2022
    Publication date: July 7, 2022
    Inventors: Stéphane BOUVIER, Sébastien IOCHEM, David DENIS
  • Publication number: 20220190101
    Abstract: An electrical device that includes a substrate; a 3D capacitor including a capacitor dielectric region of a dielectric material, a capacitor electrode region of a conductive material, the capacitor dielectric region and the capacitor electrode region being arranged at least partially inside a cavity extending in the substrate from a top face of the substrate; and a surrounding through opening in the substrate and which surrounds a surrounded substrate region, the 3D capacitor being outside of the surrounded substrate region, the surrounding through opening extending from the top face to a bottom face of the substrate, wherein inside the surrounding through opening a surrounding dielectric region of the dielectric material and a surrounding conductive region of the conductive material are arranged.
    Type: Application
    Filed: December 15, 2021
    Publication date: June 16, 2022
    Inventors: Stéphane BOUVIER, Nicolas NORMAND, Emmanuel LEFEUVRE
  • Patent number: 11309382
    Abstract: An electronic product that includes a component having a first electrode with a first surface and a pillar extending from the first surface in a first direction, the pillar having three protrusions, the three protrusions forming angles of about 120 degrees with each other around a central line of the pillar where the three protrusions meet, and the three protrusions being bent so that the pillar has a triskelion cross-section in a plane perpendicular to the first direction.
    Type: Grant
    Filed: October 16, 2020
    Date of Patent: April 19, 2022
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Stéphane Bouvier, Florent Lallemand
  • Patent number: 11164862
    Abstract: An integrated resistor-capacitor (RC) structure (400) is disclosed. The integrated RC structure includes a vertical capacitor (302,402,306) and a resistive element (308,310) disposed above the capacitor. The integrated RC structure uses a low ohmic substrate (302) to ensure a good ground return path for the capacitor. Further, a resistivity of the substrate is configured such that a top plate (306) of the capacitor provides a reference ground above a predefined frequency. The impedance of the resistive element (308,310) is matched, relative to the reference ground, to a predetermined resistance. As such, the resistance of the resistive element (308,310) can be controlled to provide an impedance controlled RC structure over a range of operating frequencies.
    Type: Grant
    Filed: January 17, 2020
    Date of Patent: November 2, 2021
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Nicolas Normand, Stéphane Bouvier
  • Publication number: 20210327867
    Abstract: RC architectures are provided that include a substrate provided with a capacitor having a thin-film top electrode portion at a surface of the substrate on one side thereof. The resistance provided in series with the capacitor is controlled by providing a contact plate, spaced from the thin-film top electrode portion, and a set of plural bridging contacts extending between, and electrically interconnecting, the thin-film top electrode portion and the contact plate. Different resistance values can be set by appropriate selection of the number of bridging contacts. The capacitor can be a three-dimensional capacitor and contacts are then provided on respective first and second sides of the substrate, which face each other in the thickness direction of the substrate.
    Type: Application
    Filed: June 30, 2021
    Publication date: October 21, 2021
    Inventors: Stéphane Bouvier, Larry Buffle, Sophie Gaborieau
  • Publication number: 20210202692
    Abstract: An electronic product having a first capacitor and a second capacitor, where the electronic product includes a semi-conductor substrate having a bottom electrode region of the first capacitor and a bottom electrode region of the second capacitor; a first dielectric layer having a first thickness arranged above the bottom electrode region of the first capacitor; a second dielectric layer having a second thickness arranged above the bottom electrode region of the second capacitor, the first thickness and the second thickness being different; a top electrode region of the first capacitor arranged above the bottom electrode of the first capacitor and above the first dielectric layer; and a top electrode region of the second capacitor arranged above the bottom electrode of the second capacitor and above the second dielectric layer.
    Type: Application
    Filed: February 23, 2021
    Publication date: July 1, 2021
    Inventors: Florent Lallemand, Stéphane Bouvier
  • Patent number: 11024701
    Abstract: An integrated electronic component for broadband biasing that includes a monolithic substrate, a capacitor structure arranged in a trench network that extends into the substrate, and a continuous track of an electrically conducting material arranged in a crater that is formed in the substrate. The continuous track has one or several turns that have decreasing turn sections, and that are supported by a slanted peripheral wall of the crater for forming an inductor.
    Type: Grant
    Filed: May 23, 2019
    Date of Patent: June 1, 2021
    Assignee: MURATA INTEGRATED PASSIVE SOLUTIONS
    Inventors: Stéphane Bouvier, Jean-René Tenailleau
  • Publication number: 20210036099
    Abstract: An electronic product that includes a component having a first electrode with a first surface and a pillar extending from the first surface in a first direction, the pillar having three protrusions, the three protrusions forming angles of about 120 degrees with each other around a central line of the pillar where the three protrusions meet, and the three protrusions being bent so that the pillar has a triskelion cross-section in a plane perpendicular to the first direction.
    Type: Application
    Filed: October 16, 2020
    Publication date: February 4, 2021
    Inventors: Stéphane Bouvier, Florent Lallemand
  • Publication number: 20200152625
    Abstract: An integrated resistor-capacitor (RC) structure (400) is disclosed. The integrated RC structure includes a vertical capacitor (302,402,306) and a resistive element (308,310) disposed above the capacitor. The integrated RC structure uses a low ohmic substrate (302) to ensure a good ground return path for the capacitor. Further, a resistivity of the substrate is configured such that a top plate (306) of the capacitor provides a reference ground above a predefined frequency. The impedance of the resistive element (308,310) is matched, relative to the reference ground, to a predetermined resistance. As such, the resistance of the resistive element (308,310) can be controlled to provide an impedance controlled RC structure over a range of operating frequencies.
    Type: Application
    Filed: January 17, 2020
    Publication date: May 14, 2020
    Inventors: Nicolas Normand, Stéphane Bouvier
  • Publication number: 20200107783
    Abstract: The invention concerns an implementable semiconductor device that includes an electrode configured to be in contact with biological tissue and at least one capacitor, and wherein the capacitor includes a capacitor electrode having a first surface facing and in contact with the electrode configured to be in contact with biological tissue.
    Type: Application
    Filed: October 3, 2019
    Publication date: April 9, 2020
    Inventors: Nicolas Normand, Stéphane Bouvier
  • Publication number: 20190280079
    Abstract: An integrated electronic component for broadband biasing that includes a monolithic substrate, a capacitor structure arranged in a trench network that extends into the substrate, and a continuous track of an electrically conducting material arranged in a crater that is formed in the substrate. The continuous track has one or several turns that have decreasing turn sections, and that are supported by a slanted peripheral wall of the crater for forming an inductor.
    Type: Application
    Filed: May 23, 2019
    Publication date: September 12, 2019
    Inventors: Stéphane Bouvier, Jean-René Tenailleau
  • Patent number: 9124286
    Abstract: Systems and methods for protecting an analog-to-digital converter (ADC) are provided. The provided systems and methods utilize comparators in a circuit of a stage of the ADC to compare a reference signal to an input signal and output one or more maximum signals when the input signal exceeds the reference signal. A decoder in the stage of the ADC may output a reset signal to another circuit in the stage of the ADC when a predetermined number of the maximum signals are received. When the other circuit receives the reset signal, the ADC may enter a protection mode to protect the ADC by ensuring that the excessive input signal is not propagated to subsequent stages.
    Type: Grant
    Filed: February 18, 2014
    Date of Patent: September 1, 2015
    Assignee: INTEGRATED DEVICE TECHNOLOGY, INC.
    Inventors: Stéphane Bouvier, Sylvain Dumont, Luis Rolindez