Abstract: Systems and methods for protecting an analog-to-digital converter (ADC) are provided. The provided systems and methods utilize comparators in a circuit of a stage of the ADC to compare a reference signal to an input signal and output one or more maximum signals when the input signal exceeds the reference signal. A decoder in the stage of the ADC may output a reset signal to another circuit in the stage of the ADC when a predetermined number of the maximum signals are received. When the other circuit receives the reset signal, the ADC may enter a protection mode to protect the ADC by ensuring that the excessive input signal is not propagated to subsequent stages.

Abstract: Systems and methods for protecting an analog-to-digital converter (ADC) are provided. The provided systems and methods utilize comparators in a circuit of a stage of the ADC to compare a reference signal to an input signal and output one or more maximum signals when the input signal exceeds the reference signal. A decoder in the stage of the ADC may output a reset signal to another circuit in the stage of the ADC when a predetermined number of the maximum signals are received. When the other circuit receives the reset signal, the ADC may enter a protection mode to protect the ADC by ensuring that the excessive input signal is not propagated to subsequent stages.

Abstract: The invention relates to an ESD protection device comprising: a first contact (10) and a second contact (20), and an electrical node (12); a bipolar transistor (6) having a base, an emitter, and a collector, the base and emitter forming a base-emitter junction, the base and collector forming a base-collector junction, the emitter being connected to the first contact (10), the collector being connected to the second contact (20), the base being connect to the electrical node (12); a first diode (1) connected between the electrical node (12) and the first contact (10), the first diode (1) comprising a first junction arranged in the same direction as the base-emitter junction, and—a second diode (2) connected between the electrical node (12) and the second contact (20), in anti-series with the first diode (1) on a path from the first contact (10) to the second contact (20), the second diode (2) comprising a second junction arranged in the same direction as the base-collector junction, wherein the bipolar transis

Abstract: The invention relates to an ESD protection device comprising: a first contact (10) and a second contact (20), and an electrical node (12); a bipolar transistor (6) having a base, an emitter, and a collector, the base and emitter forming a base-emitter junction, the base and collector forming a base-collector junction, the emitter being connected to the first contact (10), the collector being connected to the second contact (20), the base being connect to the electrical node (12); a first diode (1) connected between the electrical node (12) and the first contact (10), the first diode (1) comprising a first junction arranged in the same direction as the base-emitter junction, and—a second diode (2) connected between the electrical node (12) and the second contact (20), in anti-series with the first diode (1) on a path from the first contact (10) to the second contact (20), the second diode (2) comprising a second junction arranged in the same direction as the base-collector junction, wherein the bipolar transis

Abstract: A decode unit comprises first and second decoders respectively connected to receive bit sequences of first and second predetermined lengths. The first and second decoders operate in parallel to generate respective outputs. A switch selects one of the outputs in dependence on an instruction mode of the processor which governs the length of the bit sequence which is actually required to be decoded.

Abstract: A computer system includes instruction fetch circuitry, decode circuitry to decode instructions and identify any registers to be used and dispatch circuitry to dispatch instructions to one or more execution units, said system including emulator circuitry for debug operations which is arranged to watch data values in one or more selected registers modified during execution of the instructions, the computer circuitry further comprising a register watch store for identifying one or more registers to be watched, comparator circuitry for comparing registers identified by said decode circuitry with registers identified in said register watch store and providing a hit signal for hits in the comparison, and instruction insertion circuitry responsive to hit signals to insert in the instruction sequence to an execution unit a store instruction to store in a location accessible by the emulation circuitry the data value in a data register identified by a hit signal after execution of the instruction using the data regist

Abstract: A computer system has a memory which holds a computer program consisting of a sequence of program instructions. The format of the program instructions depends on an instruction mode of the computer system. A decoder is arranged to receive and decode program instructions. A microinstruction generator is responsive to information from the decoder to generate microinstructions according to a predetermined microinstruction format which is independent of the instruction mode of the computer system. The computer system has a plurality of parallel execution units for receiving and executing the microinstructions.

Abstract: This device finds interesting applications in the field of interface circuits for optical fibers. There is proposed in this circuit to utilize a symmetrical amplifier (19) to which an automatic gain control circuit (27) is added which is insensitive to variations of the offset voltage of this amplifier. This control circuit (27) comprises peak detectors which give the best results in a circuit of this type intended for processing signals at very high frequencies.

Abstract: A computer system for executing instructions predicated on guard indicators included in the instructions. The instructions include normal instructions, which are executed if the guard indicator is true and branch instructions, which are executed if the guard indicator is false. The computer system is operable in a branch shadow mode for comparing the guard indicator of the branch instruction with the guard indicator included in subsequent instructions and for continuing to supply instructions if the guard indicators match and for preventing supply of instructions if the guard indicators do not match. The computer system is also operable to disable the branch shadow mode when the branch instruction has been determined such that the branch is taken or not by resolving the status of the guard indicator.

Abstract: A decode unit (20) decodes instructions in a processor. These, instructions include instructions of a first length in a first instruction mode and instructions of a second, shorter length in a second instruction mode. The decode unit has decoding circuitry (50-60) which decode the instructions. A register holds the instruction mode and generates an instruction mode signal. Switching circuitry (MUX6,MUX7) is responsive to the instruction mode signal to output decoded instructions from the decode unit depending on the instruction mode. A detector (70) is provided for detecting a length change instruction of the second, shorter length while in the second instruction mode which indicates that the subsequent instruction is of the first length. The detector also temporarily alters the state of the instruction mode signal to allow the first length instructions to be decoded without changing the instruction mode held in the register.

Abstract: The present invention relates to a modulation device MD, which is designed to produce an output signal Vout comprising a succession of pulses. According to the invention, a device of this type includes: two transistors T1 and T2, which are arranged as a differential pair; a capacitive element C, which is connected between the two transistors T1 and T2; adjusting means LC1, LC2, UC1, UC2, in order to adjust the potential of at least one of the terminals of the capacitive element C; and comparing means CMP, which supply the output signal Vout, which is representative of the sign of the voltage Vc, which is present at the terminals of the capacitive element C. By means of a simple and substantially analog structure, the invention permits rapid, flexible control of the width of the pulses of the output signal Vout.

Abstract: This device finds interesting applications in the field of interface circuits for optical fibers. There is proposed in this circuit to utilize a symmetrical amplifier (19) to which an automatic gain control circuit (27) is added which is insensitive to variations of the offset voltage of this amplifier. This control circuit (27) comprises peak detectors which give the best results in a circuit of this type intended for processing signals at very high frequencies.

Abstract: The present invention relates to a modulation device MD, which is designed to produce an output signal Vout comprising a succession of pulses.

Abstract: A computer system includes instruction fetch circuitry, decode circuitry to decode instructions and identify any registers to be used and dispatch circuitry to dispatch instructions to one or more execution units, said system including emulator circuitry for debug operations which is arranged to watch data values in one or more selected registers modified during execution of the instructions, the computer circuitry further comprising a register watch store for identifying one or more registers to be watched, comparator circuitry for comparing registers identified by said decode circuitry with registers identified in said register watch store and providing a hit signal for hits in the comparison, and instruction insertion circuitry responsive to hit signals to insert in the instruction sequence to an execution unit a store instruction to store in a location accessible by the emulation circuitry the data value in a data register identified by a hit signal after execution of the instruction using the data regist

Abstract: A control circuit controls the power supply to an electric motor and, comprises a power transistor NM of the NMOS type and a power transistor PM of the PMOS type arranged between two supply terminals VCC and GND, their intermediate node forming an output coupled to a coil Ei of the motor. The well B of the transistor PM is coupled to supply terminal VCC via an isolation diode ID, which has its anode connected to supply terminal VCC and has its cathode connected to the well B. The isolation diode ID ensures that the coil Ei is not short-circuited by the parasitic drain-well diode D of the transistor PM in case of a sudden power failure.

Abstract: An interface circuit makes it possible, starting from an input signal varying between a reference level (VR) available on a first terminal and a first voltage level (V1), to deliver an output signal varying between this reference level (VR) and a second voltage level (V2) available on a second terminal. The circuit includes first and second branches each including first and second serially connected complementary transistors and a third branch with serially connected first and second transistors. First and second inverters couple the input terminal to respective control electrodes of the second transistors in the second and third branches. The inverters have response times chosen so that the two transistors of the third branch are never on simultaneously. Thus, short-circuiting the transistors of the second branch during the transient regime creates almost no current spike.