Abstract: Systems and methods presented herein provide for data storage for a plurality of host systems. In one embodiment, a storage system comprises a storage unit, and a controller. The controller is operable to process a write I/O request from a first of the host systems, to determine an identity of the first host system from the write I/O request, to encrypt data of the write I/O request based on the identity of the first host system, to locate a storage space allocated to the first host system in the storage unit, to determine that a size of the data of the write I/O request requires more storage space than currently allocated to the first host system, to increase the storage space allocated to the first host system by the size of the data of the write I/O request, and to write the encrypted data to the storage unit.

Abstract: Systems and methods for encryption key shredding to protect non-persistent data are described. In one embodiment, the storage system device may include a storage drive and a controller. In some embodiments, the controller may be configured to power on the storage drive, identify an encryption key on the storage drive created upon powering on the storage drive, and encrypt data in a cache of the storage drive using the encryption key. In some embodiments, the controller may be configured to power off the storage drive and delete the encryption key upon powering off the storage drive. In some cases, the storage drive may include at least one of a solid state drive and a hard disk drive. In some embodiments, the storage drive may include a hybrid storage drive that includes both a solid state drive and a hard disk drive.

Abstract: Systems and methods for encrypting system level data structures are described. In one embodiment, a storage system may include a storage drive and at least one controller for the storage drive. In some embodiments, the at least one controller may be configured to identify user data assigned to be stored on the storage drive, encrypt the user data, identify a system data structure generated in relation to the user data, and encrypt the system data structure. In some cases, the data structure may include at least one of metadata, system data, and data encapsulation relative to the user data. In some embodiments, the user data and the data structure may be encrypted with one or more encryption keys programmed on the storage drive.

Abstract: Systems and methods for hash authenticated data are described. In one embodiment, the storage device includes a storage drive and/or a controller. In some embodiments, the controller is configured to identify data to be authenticated, compute a first hash of the data using a hash function, detect a trigger event associated with the storage drive, and authenticate, after the trigger event, the data based at least in part on the first hash of the data.

Abstract: Systems and methods for enhanced read recovery based on write time information are described. In one embodiment, the systems and methods include opening a block of flash memory cells for programming, tracking a block open time, and performing a read operation of a programmed page from the block based at least in part on the block open time. In some embodiments, the block includes a plurality of pages, each page including a plurality of flash memory cells. In some cases, the block open time includes an amount of time between the block opening for programming to a time the block closes for programming.

Abstract: In one embodiment, a network device is disclosed. For example, in one embodiment of the present invention, the device comprises a processor and a core memory having a receive buffer and a transmit buffer. The device comprises a bus coupled to the processor and the core memory. The device comprises at least one co-processor coupled to the core memory via a direct link, wherein the at least one co-processor is capable of accessing at least one of: the receive buffer, or the transmit buffer, without assistance from the processor.

Abstract: In one embodiment, a device is disclosed. For example, in one embodiment of the present invention, the device comprises a first memory stage for storing a plurality of pointer values associated with a plurality of buffers, wherein the plurality of buffers is associated with a plurality of logical channels. The device further comprise a second memory stage, wherein an access address to the second memory stage is formed from a concatenation of one of the plurality of pointer values and a channel number corresponding to one of the plurality of logical channels.

Abstract: In one embodiment, a device is disclosed. For example, in one embodiment of the present invention, the device comprises a memory core having a shared buffer, and an arbitration logic module for receiving a destination ready signal from a processing source of a plurality of processing sources. The device also comprises at least one pipeline stage for storing at least one piece of data read from the shared buffer, and at least one matching pipeline stage storing at least one valid signal associated with the at least one piece of data read from the shared buffer. The device also comprises a counter for storing a value, wherein the value represents a number of pieces of data read from the shared buffer, but have not been delivered to the processing source.

Abstract: A multi-pass method of implementing a testbench can include, during a pre-processing pass, randomly selecting a configuration of the testbench and generating configuration data specifying the randomly selected configuration of the testbench. During a subsequent processing pass, the method can include compiling the testbench in accordance with the configuration data. Simulation can be performed using the testbench.

Abstract: A circuit configuration for a pipeline core to be implemented in a programmable integrated circuit (IC) is dynamically specified by providing a single code set embodying an expanded netlist representative of a dynamic circuit configuration of the pipeline core. The code set, which includes one or more parameter variables that determine the length and width of the implemented pipeline core, is synthesized by setting the parameter variables to selected constant values to generate a reduced netlist embodying a static circuit configuration for the implemented pipeline core.

Abstract: A method of evaluating a design under test (DUT) can include executing a testbench involving the DUT and, during execution of the testbench, estimating an amount of time needed to perform a first transaction with the device under test according to resolved variables. The method also can include setting a timer with the estimated amount of time needed to perform the first transaction and invoking the first transaction with the device under test. Responsive to expiration of the timer, an indication as to whether the first transaction completed execution can be provided.

Abstract: A buffer management system for a data processing system can include a plurality of tokens wherein each token is associated with one of a plurality of buffers, and a plurality of first-in-first-out (FIFO) memories. Each FIFO memory can be associated with a stage of the data processing system and is configured to store at least one of the tokens. The buffer management system also can include control logic configured to determine a state of one or more selected buffers and transfer the token associated with the selected buffer from a source FIFO memory to a target FIFO memory. The target FIFO memory can be selected according to the state of the selected buffer.

Abstract: Methods of generating a PLD design implementation according to a design architecture tailored to specified requirements. A hardware description language (HDL) description for the PLD design includes at least one parameter value for the PLD design that will affect the preferred implementation of the design. This parameter value is passed to a high-level language (HLL) function, which is used to determine a tailored design architecture in accordance with the specified needs of the target application. The HLL function returns data specifying the tailored design architecture. This data is used in generating an implementation of the PLD design that follows the constraints imposed by the tailored design architecture. The result can be, for example, a logic gate representation of the PLD design, a netlist of the design, or a bitstream implementing the design in a target PLD.

Abstract: The present invention provides a pushback FIFO architecture that enables a value that has been unloaded from the FIFO to be pushed back into the FIFO at the beginning of the data stream if a determination as made that the data value should not have been unloaded from the FIFO. Therefore, the pushed back data value will be the first data value unloaded from the FIFO on the following read cycle. Because the data value that should not have been unloaded is not lost, and is placed at the beginning of the data value sequence, the pushback FIFO enables speculative unloads of data values from the FIFO to be performed.

Abstract: A multi-pass method of implementing a testbench can include, during a pre-processing pass, randomly selecting a configuration of the testbench and generating configuration data specifying the randomly selected configuration of the testbench. During a subsequent processing pass, the method can include compiling the testbench in accordance with the configuration data. Simulation can be performed using the testbench.

Abstract: Computer-implemented methods of mapping a logical representation of a memory to physical memory, e.g., in a programmable logic device (PLD). The logical representation of the memory is input into the computer, which generates an initial solution (e.g., a column-based solution) for the memory. In a column-based solution, the primitives are arranged such that each column includes only one type of primitive. The column-based solution generated in this step uses the minimum number of primitives attainable by a column-based approach. The column-based solution is then modified to reduce multiplexing, e.g., by replacing two primitives that are cascaded in depth with two primitives that are cascaded in width. In some embodiments, the total number of primitives can be reduced by the modification. The resulting physical representation of the memory is then output, and can be utilized, if desired, to create an implementation of the memory targeted to a PLD.

Abstract: A multithreaded testbench configured to verify a device under test defined by hardware description language logic can include a test case for the testbench executing within a master thread and a generator executing within a sub-thread thread of the master thread. The generator can be configured to create test vectors to be provided to the device under test. The testbench further can include one or more additional modules executing within additional sub-thread(s) of the master thread and a command queue. The additional module(s) can interact with the device under test. The command queue can be configured to store a plurality of commands registered by the master thread. The generator can obtain individual ones of the plurality of commands from the command queue for execution.

Abstract: Apparatuses for binary priority encoding are described. A binary priority encoder (100, 100L) includes a data input bus (139), a first logic tree (110) coupled to receive data from the input bus (139), and a second logic tree (130) coupled to receive a portion of the data from the input bus (139). The first logic tree (110) is configured to provide a flag signal (154) indicating whether at least one bit of the data is active. The first logic tree (110) is configured to provide control signals. The second logic tree (130) is coupled to receive the control signals. The second logic tree (130) is configured to select first partial addresses from the portion of the data responsive to the control signals. The control signals are further provided to the second logic tree (130) as second partial addresses.

Abstract: The present invention provides a pushback FIFO architecture that enables a value that has been unloaded from the FIFO to be pushed back into the FIFO at the beginning of the data stream if a determination as made that the data value should not have been unloaded from the FIFO. Therefore, the pushed back data value will be the first data value unloaded from the FIFO on the following read cycle. Because the data value that should not have been unloaded is not lost, and is placed at the beginning of the data value sequence, the pushback FIFO enables speculative unloads of data values from the FIFO to be performed.

Abstract: The present invention provides a pushback FIFO architecture that enables a value that has been unloaded from the FIFO to be pushed back into the FIFO at the beginning of the data stream if a determination as made that the data value should not have been unloaded from the FIFO. Therefore, the pushed back data value will be the first data value unloaded from the FIFO on the following read cycle. Because the data value that should not have been unloaded is not lost, and is placed at the beginning of the data value sequence, the pushback FIFO enables speculative unloads of data values from the FIFO to be performed.