Abstract: A method for accurately analyzing the timing of a clock network on a piecemeal basis in an integrated circuit clock tree is presented. In accordance with the invention, the time delay of each individual subcircuit between an identified clock network node and an identified receiving endpoint may be individually determined. Tags are associated with the connection points of a child block and its parent block. A connection tool uses the tags to match up the connection points of the parent block to the respective connection points in the child block to allow a simulation tool to include the clock signal timing data of the child block in simulating the clock performance of the parent block.

Abstract: A method for allowing in-place programming of clock buffer delays of clock buffers in an integrated circuit clock tree is presented. The clock tree comprises at least one clock driver connected between a clock driver input line and a clock driver output line. Each clock driver comprises a plurality of clock buffers connected in series between the clock driver input line and, potentially, the clock driver output line. Metal is reserved in intervening metal layers within a clock driver block between the clock driver input line and the input of a first one of said plurality of clock buffers in the variable clock buffer chain. Metal is reserved on one or more metal layers for connecting the output of each of the clock buffers in the clock buffer chain to the clock driver output line. The metal layers are partitioned into one or more programming layers and one or more non-programming layers.

Abstract: A method for accurately analyzing the timing of a clock network on a piecemeal basis in an integrated circuit clock tree is presented. In accordance with the invention, the time delay of each individual subcircuit between an identified clock network node and an identified receiving endpoint may be individually determined. Tags are associated with the connection points of a child block and its parent block. A connection tool uses the tags to match up the connection points of the parent block to the respective connection points in the child block to allow a simulation tool to include the clock signal timing data of the child block in simulating the clock performance of the parent block.

Abstract: The present invention provides a pushback FIFO architecture that enables a value that has been unloaded from the FIFO to be pushed back into the FIFO at the beginning of the data stream if a determination as made that the data value should not have been unloaded from the FIFO. Therefore, the pushed back data value will be the first data value unloaded from the FIFO on the following read cycle. Because the data value that should not have been unloaded is not lost, and is placed at the beginning of the data value sequence, the pushback FIFO enables speculative unloads of data values from the FIFO to be performed.

Abstract: A non-destructive read FIFO configured to enable data that has been read from an address in the FIFO in a first read cycle to be re-read from the same address in the FIFO in a subsequent read cycle. When the FIFO is full, data stored at the addresses in the FIFO will be read out of the FIFO multiple times in a sequence in which the data was written into the FIFO. The number of times that the stored data is read out of the FIFO in the sequence in which the data was written into the FIFO is preselected. Therefore, the FIFO can be used to cache a loop of instructions that are to be executed a particular number of times.