Abstract: A blank or tray formed therefrom and including a bottom wall and side walls with the end walls formed by an end panel having a slit therein and by end flaps connected to the side walls and provided with upper and lower tabs. The structure of each flap is such that it may be folded along a diagonal fold-line to permit the upper tab to be moved into a position to be slid through the slot in the adjacent end panel and then the flap forced into a straightened position with the bottom tab received in a hole in the bottom wall. If desired, a lid assembly may be provided, the lid assembly having tabs thereon adapted to be received within extensions of the slit through which the top tab is received.

Abstract: Push-pop stack and counters added to automatic processor's program addressing and execution logic. A certain instruction, typically a load counter instruction, "pushes" the contents of the program counter (instruction address register) onto the stack (that is, loads the stack in the direction from top toward bottom). Other certain instructions, such as decrement and test counter, or special bits in all instructions decrement the last loaded counter's value by one and test for zero counter value. If the test is false, the instruction address register's contents are replaced by the top stack word and the program loop is repeated. The program loop is thus repeated until the test is true. When the test is true, the program counter addresses the next instruction in sequence and the stack is popped (its contents are shifted in the direction from the bottom toward the top of the stack), the top stack word being lost since the program loop will not be repeated.

Abstract: Two-unit architecture for a microprocessor having one unit to execute program instructions and another unit to fetch the instructions in their proper sequence, being arranged to permit the overlap of fetch and execute cycles to increase program execution speed. Each unit includes a register array for storing operands or addresses, each array having two independent read ports and two independent write ports. In the execution unit, the register array stores operands, read from a memory by the fetch unit, which are applied to an arithmetic-logic unit (ALU), and stores the result from the ALU. In the fetch unit, the array is used to store indirect addresses, which can be incremented or decremented in an adder.

Abstract: A blank and a tray formed therefrom and having end walls each formed by a first end panel foldably connected to a bottom panel, a first top panel, a second top panel and a second end panel all foldably interconnected by a set of substantially parallel fold lines thereby to provide a multilayered vertical wall and a top platform of at least a double thickness. Preferably, a projecting nesting panel is formed in the second top wall and is connected directly to the second end panel, a slot is provided in the first top panel adjacent its connection with the first end panel and said nesting panel is projected through said slot when said blank is erected to form a tray.

Abstract: An ornamental design for a telephone is disclosed in which the telephone is arcuate and includes a pushbutton dial that has a planar face and rectangular pushbuttons. The longitudinal walls on each side of the dial vary in height, the walls having a greater height at their ends than in the middle. In addition, the portion of the set between the dial and the mouthpiece end of the set includes a planar inclined ramp that extends at an angle to both the flat surface of the dial and the curved surface of the set.