Abstract: In a circuit that reduces power consumption in an array system of memory cells accessible in parallel, a local evaluation circuit is connected to a memory cell and a global bit line of the array system of memory cells. A selection circuitry splits the global bit line into an upper part and a lower part of the global bit line. The selection circuitry is adapted to receive an early set prediction signal and to connect the upper part of the global bit line to the lower part of the global bit line based on the early set prediction signal. The early set prediction signal indicates whether a set of memory cells, which include the memory cell, is being read. The circuit also includes a N:1 multiplexer connected to the lower part of the global bit line to receive the lower part of the global bit line as input.

Abstract: A method for processing a plate workpiece supported on a workpiece support. The method includes moving a tool die and a tool punch along a stroke axis and toward a processing position above a support plane of the workpiece support. The processing position corresponds to a region of the plate workpiece having a formed shape, which extends upwardly from the support plane of the workpiece support.

Abstract: In a circuit that reduces power consumption in an array system of memory cells accessible in parallel, a local evaluation circuit is connected to a memory cell and a global bit line of the array system of memory cells. A selection circuitry splits the global bit line into an upper part and a lower part of the global bit line. The selection circuitry is adapted to receive an early set prediction signal and to connect the upper part of the global bit line to the lower part of the global bit line based on the early set prediction signal. The early set prediction signal indicates whether a set of memory cells, which include the memory cell, is being read. The circuit also includes a N:1 multiplexer connected to the lower part of the global bit line to receive the lower part of the global bit line as input.

Abstract: In some aspects of the invention, tool components for processing of plate-like workpieces, the tool component include an end face adjoined by a tool region provided for regrinding, the tool region being configured to undergo regrinding as a result of wear; and at least one identification mark located on the tool component to indicate the amount of shortening of the tool region as a result of regrinding.

Abstract: The invention relates to disc-shaped compensation shims for compensating for the shortening of a tool die or a tool stamp due to regrinding. The shim includes a coding indicating a thickness of the tooling shim, the tooling shim being configured for use with a tool die or tool stamp to compensate for shortening of the tool die or tool stamp resulting from regrinding. The invention also relates to tool arrangements having at least one such shim, and to machine tools having such tool arrangements.

Abstract: In some aspects of the invention, a punching tool includes a punching stamp including a stamp shaft and an axial stop; and an adjustment ring having a center opening configured to receive the stamp shaft and abut the axial stop, where a first mark is located along a cylindrical portion of the stamp shaft adjoining the axial stop, and at least a portion of the first mark remains visible when the adjustment ring is abutted against the axial stop.

Abstract: A loading and unloading unit for sheet metal providing a first tool holder is provided. Therewith, sheet metal processing tools may be passed from a first tool magazine that is attached to a fixed unit of the loading and unloading unit to a second tool holder integrated in a sheet metal processing machine or to a tool fixture of the sheet metal processing machine, and, thus, the number of tools automatically exchangeable in the sheet metal processing machine can be increased to create a more efficient and space-saving manufacturing process.

Abstract: A plate workpiece processing method includes utilizing one or more cutting devices of a machine tool to perform first and second cutting operations on a plate workpiece. During the first cutting operation, the workpiece is moved relative to cutting device(s) used for the first cutting operation, at least two cut-outs are partially formed in the workpiece with only a common residual connection left that jointly connects the partially formed cut-outs to a remaining portion of the workpiece and that is shortened along one or more cutting lines of the second cutting operation to a size that is larger than a working area of the cutting device(s) used for the second cutting operation. During the second cutting operation, the workpiece is maintained stationary supported by the machine tool, the shortened common residual connection is severed along the cutting line(s) to completely separate the cut-outs from the remaining portion of the workpiece.

Abstract: A method for testing memory elements of an integrated circuit with an array built in self test (ABIST) comprises providing an ABIST interface to interface between an ABIST engine and a plurality of latches of a memory element under test, providing a multiplex (MUX) stage adjacent a scan input port of each latch, providing functional signal inputs to a data input port of the latches, setting the latches to an ABIST mode by activating an ABIST enable signal and delivering the ABIST enable signal to each of the latches, generating a plurality of ABIST test signals with the ABIST engine, applying the ABIST test signals in parallel to the scan input ports of the latches, determining whether one or more test patterns have been executed, and setting the latches to a normal run mode by deactivating the ABIST enable signal.

Abstract: A tool system is provided that has a stamp or punch adapter including eccentrically positioned stamp receptacles. This system permits a simple exchange of tool inserts in the stamp adapter. These tool inserts are also usable in another tool system. The system also permits combining the stamp adapter with a stamp shaft, which can also be used in another tool system. These features permit stamping (and punching) with minimal tooling and retooling efforts.

Abstract: A method for testing memory elements of an integrated circuit with an array built in self test (ABIST) comprises providing an ABIST interface to interface between an ABIST engine and a plurality of latches of a memory element under test, providing a multiplex (MUX) stage adjacent a scan input port of each latch, providing functional signal inputs to a data input port of the latches, setting the latches to an ABIST mode by activating an ABIST enable signal and delivering the ABIST enable signal to each of the latches, generating a plurality of ABIST test signals with the ABIST engine, applying the ABIST test signals in parallel to the scan input ports of the latches, determining whether one or more test patterns have been executed, and setting the latches to a normal run mode by deactivating the ABIST enable signal.

Abstract: A method for processing a plate workpiece supported on a workpiece support. The method includes moving a tool die and a tool punch along a stroke axis and toward a processing position above a support plane of the workpiece support. The processing position corresponds to a region of the plate workpiece having a formed shape, which extends upwardly from the support plane of the workpiece support.

Abstract: A machine tool that includes a workpiece support and a punching die. The punching die includes a support surface, for supporting a workpiece to be processed, and a discharging slope. The discharging slope is configured such that a workpiece part, severed from a workpiece supported on the support surface of the punching die, is displaced, in at least one of a rotational, tilting, or linear movement, from a processing position at least partially overlying the discharging slope toward a removal position on the discharging slope. The discharging slope is also configured such that a workpiece part, severed from a workpiece supported on the support surface of the punching die, is directed, in a sliding movement, toward a discharging position located beneath the support surface and adjacent the punching die.

Abstract: A plate workpiece processing method for obtaining at least two workpiece cut-outs from a plate workpiece. The method includes utilizing one or more cutting devices of a machine tool to perform a first cutting operation and a second cutting operation on a plate workpiece. During the first cutting operation, with the plate workpiece moving relative to the cutting device or cutting devices used for the first cutting operation, at least two workpiece cut-outs are partially formed in the plate workpiece with only a common residual connection being left that jointly connects the partially formed workpiece cut-outs to a remaining portion of the plate workpiece and that is shortened along one or more cutting lines of the second cutting operation to a size that fits within a working area of the cutting device or cutting devices used for the second cutting operation.

Abstract: An asymmetrical random access memory cell (1) including cross coupled inverters (2, 3) which are driven at their nodes (22, 32) by separate bit-lines (blt, blc) of a pair of complementary bit-lines, which are connected via a pass-transistors (21, 31), wherein said cross coupled inverters (2, 3) have different switching thresholds and exhibit asymmetrical physical behaviours, wherein an additional pass-transistor (4) is provided in series to one of the pass-transistors (21) between one of the nodes (22) and its dedicated bit-line (blc). Further the invention relates to a random access memory including such memory cells and to a method of operating such a memory.

Abstract: A method and memory circuit comprising a plurality of cells accessible by word lines and bit lines is described, wherein each cell includes a group of six transistors adapted to both store a bit inserted into the cell during a write operation and affect a signal asserted during a read operation on a bit line coupled to the cell such that the affected signal matches a value of the bit stored in the cell, wherein the word lines and bit lines of the memory are divided into sections assigned to groups of equal numbers of cells, wherein said sections are individually accessible for read or write operations such that one cell of a group can be read simultaneously while writing another cell of the group.

Abstract: Asymmetrical random access memory cell, memory comprising asymmetrical memory cells and method to operate such a memory The invention relates to an asymmetrical random access memory cell (1) comprising cross coupled inverters (2, 3) which are driven at their nodes (22, 32) by separate bit-lines (b1t, b1c) of a pair of complementary bit-lines, which are connected via a pass-transistors (21, 31), wherein said cross coupled inverters (2, 3) have different switching thresholds and exhibit asymmetrical physical behaviours, wherein an additional pass-transistor (4) is provided in series to one of the pass-transistors (21) between one of the nodes (22) and its dedicated bit-line (blc). Further the invention relates to a random access memory comprising such memory cells and to a method of operating such a memory.

Abstract: A method and a device for decoding an address word into word-line signals. A plurality of address lines feed the address word into a plurality of decoding blocks each associated to a particular address in the address space formed by the address word for generating a respective word-line signals, whereby each of the decoding blocks is connected to the plurality of address lines. At least one decoding block associated to a predetermined address in the address space formed by the address word is omitted, so that none of the generated word lines is switched to the active state, whenever the predetermined address word is inputted over the plurality of address lines.

Abstract: A method and a device for decoding an address word into word-line signals. A plurality of address lines feed the address word into a plurality of decoding blocks each associated to a particular address in the address space formed by the address word for generating a respective word-line signals, whereby each of the decoding blocks is connected to the plurality of address lines. At least one decoding block associated to a predetermined address in the address space formed by the address word is omitted, so that none of the generated word lines is switched to the active state, whenever the predetermined address word is inputted over the plurality of address lines.

Abstract: A method and a device for decoding an address word into word-line signals. A plurality of address lines feed the address word into a plurality of decoding blocks each associated to a particular address in the address space formed by the address word for generating a respective word-line signals, whereby each of the decoding blocks is connected to the plurality of address lines. At least one decoding block associated to a predetermined address in the address space formed by the address word is omitted, so that none of the generated word lines is switched to the active state, whenever the predetermined address word is inputted over the plurality of address lines.