Abstract: A method and a device for decoding an address word into word-line signals. A plurality of address lines feed the address word into a plurality of decoding blocks each associated to a particular address in the address space formed by the address word for generating a respective word-line signals, whereby each of the decoding blocks is connected to the plurality of address lines. At least one decoding block associated to a predetermined address in the address space formed by the address word is omitted, so that none of the generated word lines is switched to the active state, whenever the predetermined address word is inputted over the plurality of address lines.

Abstract: The invention describes a high-performance static logic compatible multiport latch. The latch is controlled by at least a first and a second clock (CLK 1, CLK 2), which consist of at least first and second data input ports (107, 111) with together at least three data inputs (DATA 1.1, . . . , DATA 1.n, DATA 2.1, . . . , DATA 2.n) and at least one data output (OUT). The first clock (CLK 1) controls whether data (DATA1.1, . . . , DATA 1.n) applied to the first data input ports (107) is stored in or clocked through the latch (100), the second clock (CLK 2) controls whether data (DATA 2.1, . . . , DATA 2.n) applied to the second data input ports (111) is stored in or clocked through the latch, and either the first clock (CLK 1) or the second clock (CLK 2) clocks data into the latch at the same time.

Abstract: The invention describes a high-performance static logic compatible multiport latch. The latch is controlled by at least a first and a second clock (CLK 1, CLK 2), which consist of at least first and second data input ports (107, 111) with together at least three data inputs (DATA 1.1, . . . , DATA 1.n, DATA 2.1, . . . , DATA 2.n) and at least one data output (OUT). The first clock (CLK 1) controls whether data (DATA1.1, . . . , DATA 1.n) applied to the first data input ports (107) is stored in or clocked through the latch (100), the second clock (CLK 2) controls whether data (DATA 2.1, . . . , DATA 2.n) applied to the second data input ports (111) is stored in or clocked through the latch, and either the first clock (CLK 1) or the second clock (CLK 2) clocks data into the latch at the same time.

Abstract: The invention relates to a memory device comprising a set of word decoders W, a set of wordline drivers WL, a plurality of switches S to connect a subset of the wordline drivers to the set of word decoders and storage means 5 for the storage of information indicative of a defective wordline. The wordline drivers include a predefined subset of wordline drivers which are to be used when none of the wordlines are defective and a plurality of second subsets of wordline drivers which are to be used when one of the wordlines is defective. The memory device further includes logic means 4 for logically and permanently assigning one of the subsets to the set of word decoders in response to the information stored in the storage means, by controlling the switches S to connect one of the second subsets of wordline drivers to the set of word decoders.