Patents by Inventor Stefan Cosemans
Stefan Cosemans has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11699482Abstract: A compute cell for in-memory multiplication of a digital data input and a balanced ternary weight, and an in-memory computing device including an array of the compute cells, are provided. In one aspect, the compute cell includes a set of input connectors for receiving modulated input signals representative of a sign and a magnitude of the data input, and a memory unit configured to store the ternary weight. A logic unit connected to the set of input connectors and the memory unit receives the data input and the ternary weight. The logic unit selectively enables one of a plurality of conductive paths for supplying a partial charge to a read bit line during a compound duty cycle of the set of input signals as a function of the respective signs of data input and ternary weight, and disables each of the plurality of conductive paths if at least one of the ternary weight and data input have zero magnitude.Type: GrantFiled: September 8, 2021Date of Patent: July 11, 2023Assignee: IMEC vzwInventors: Stefan Cosemans, Ioannis Papistas, Peter Debacker
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Patent number: 11651816Abstract: There is provided a method for accessing a memory cell of a plurality of memory cells that are part of a memory unit, the memory cells being grouped into a plurality of memory cell groups, wherein each memory cell group is associated with one or more local bit lines with each of the one or more local bit lines being operatively connected to a corresponding global bit line via a passgate comprising a PMOS transistor. The method comprises connecting each of the one or more local bit lines to the corresponding global bit line by decreasing a gate voltage that is applied to a gate of the corresponding PMOS transistor to a value that is sufficient to allow the PMOS transistor to conduct, wherein the value of the gate voltage that is sufficient to allow the PMOS transistor to conduct is either a positive or negative voltage.Type: GrantFiled: July 22, 2021Date of Patent: May 16, 2023Assignee: SURECORE LIMITEDInventors: Stefan Cosemans, Bram Rooseleer
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Patent number: 11342261Abstract: Integrated circuit comprising an interconnection system comprising at least one multilevel layer comprising first parallel electrically conductive lines, the multilevel layer comprising at least three levels forming a centerline level, an upper extension line level, and a lower extension line level the levels providing multilevel routing tracks in which the lines extend.Type: GrantFiled: December 19, 2019Date of Patent: May 24, 2022Assignee: IMEC VZWInventors: Stefan Cosemans, Julien Ryckaert, Zsolt Tokei
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Patent number: 11276430Abstract: A storage device including a tape configured to store data is disclosed. The tape includes a plurality of first regions with a first dielectric constant and a plurality of second regions with a second dielectric constant that is higher than the first dielectric constant. The first regions and the second regions are arranged in an alternating manner along the length of the tape. Further, the storage device includes one or more actuators configured to apply an electrical field across the width of the tape, in order to move the tape in length direction. Further, the storage device includes one or more data heads configured to read and/or write data from and/or to the tape.Type: GrantFiled: December 9, 2020Date of Patent: March 15, 2022Assignee: IMEC vzwInventor: Stefan Cosemans
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Publication number: 20220076737Abstract: A compute cell for in-memory multiplication of a digital data input and a balanced ternary weight, and an in-memory computing device including an array of the compute cells, are provided. In one aspect, the compute cell includes a set of input connectors for receiving modulated input signals representative of a sign and a magnitude of the data input, and a memory unit configured to store the ternary weight. A logic unit connected to the set of input connectors and the memory unit receives the data input and the ternary weight. The logic unit selectively enables one of a plurality of conductive paths for supplying a partial charge to a read bit line during a compound duty cycle of the set of input signals as a function of the respective signs of data input and ternary weight, and disables each of the plurality of conductive paths if at least one of the ternary weight and data input have zero magnitude.Type: ApplicationFiled: September 8, 2021Publication date: March 10, 2022Inventors: Stefan Cosemans, Ioannis Papistas, Peter Debacker
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Publication number: 20210390997Abstract: A method of operating a voltage-controlled magnetic anisotropy (VCMA) magnetic tunnel junction (MTJ) device is disclosed. The MTJ device is switchable between a first resistance state and a second resistance state. A first threshold voltage for switching the MTJ device from the second resistance state to the first resistance state is lower than a second threshold voltage for switching the MTJ device from the first resistance state to the second resistance state. The method includes applying a first voltage pulse across the MTJ device with an amplitude having an absolute value equal to or greater than the first threshold voltage and lower than the second threshold voltage, thereby setting the MTJ device to the first resistance state regardless of whether the MTJ device initially is in the first or second resistance state.Type: ApplicationFiled: June 10, 2021Publication date: December 16, 2021Inventors: Woojin KIM, Yueh Chang WU, Stefan COSEMANS, Gouri Sankar KAR
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Publication number: 20210350841Abstract: There is provided a method for accessing a memory cell of a plurality of memory cells that are part of a memory unit, the memory cells being grouped into a plurality of memory cell groups, wherein each memory cell group is associated with one or more local bit lines with each of the one or more local bit lines being operatively connected to a corresponding global bit line via a passgate comprising a PMOS transistor. The method comprises connecting each of the one or more local bit lines to the corresponding global bit line by decreasing a gate voltage that is applied to a gate of the corresponding PMOS transistor to a value that is sufficient to allow the PMOS transistor to conduct, wherein the value of the gate voltage that is sufficient to allow the PMOS transistor to conduct is either a positive or negative voltage.Type: ApplicationFiled: July 22, 2021Publication date: November 11, 2021Inventors: Stefan COSEMANS, Bram ROOSELEER
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Publication number: 20210310981Abstract: In a first aspect, the present disclosure relates to a system for addressing nanoelectrodes in a nanoelectrode array, the system including an array of electrode cells, each electrode cell including: an access transistor having a gate resistively coupled to a word line, a source resistively coupled to a bit line, and a drain, and a storage circuit resistively coupled to the drain and including a nanoelectrode.Type: ApplicationFiled: March 22, 2021Publication date: October 7, 2021Inventors: Olivier Henry, Arnaud Furnemont, Stefan Cosemans
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Patent number: 11100978Abstract: There is provided a method for accessing a memory cell of a plurality of memory cells that are part of a memory unit, the memory cells being grouped into a plurality of memory cell groups, wherein each memory cell group is associated with one or more local bit lines with each of the one or more local bit lines being operatively connected to a corresponding global bit line via a passgate comprising a PMOS transistor. The method comprises connecting each of the one or more local bit lines to the corresponding global bit line by decreasing a gate voltage that is applied to a gate of the corresponding PMOS transistor to a value that is sufficient to allow the PMOS transistor to conduct, wherein the value of the gate voltage that is sufficient to allow the PMOS transistor to conduct is either a positive or negative voltage.Type: GrantFiled: June 2, 2017Date of Patent: August 24, 2021Assignee: Surecore LimitedInventors: Stefan Cosemans, Bram Rooseleer
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Publication number: 20210174832Abstract: A storage device including a tape configured to store data is disclosed. The tape includes a plurality of first regions with a first dielectric constant and a plurality of second regions with a second dielectric constant that is higher than the first dielectric constant. The first regions and the second regions are arranged in an alternating manner along the length of the tape. Further, the storage device includes one or more actuators configured to apply an electrical field across the width of the tape, in order to move the tape in length direction. Further, the storage device includes one or more data heads configured to read and/or write data from and/or to the tape.Type: ApplicationFiled: December 9, 2020Publication date: June 10, 2021Inventor: Stefan Cosemans
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Method for manufacturing a magnetic tunnel junction device and device manufactured using such method
Patent number: 11004898Abstract: A magnetic tunnel junction memory device is disclosed. In one aspect, the memory device comprises a substrate, a first memory element, and a second memory element, wherein the first memory element and the second memory element are formed of a stack comprising at least a first layer and a second layer, the first layer being arranged between the substrate and the second layer. The memory device further comprises a first selector device arranged to contact the first memory element, and a second selector device arranged to contact the second memory element, wherein the first selector device and the second selector device are arranged in or above the second layer. The first memory element and the second memory element are interconnected via the first layer, and are separated from each other by a trench formed in the second layer.Type: GrantFiled: December 28, 2018Date of Patent: May 11, 2021Assignee: IMEC vzwInventors: Gouri Sankar Kar, Stefan Cosemans -
Patent number: 10878864Abstract: There is provided a multiple data rate memory comprising a clock splitting circuit and a multiplexing address latch. The clock splitting circuit is configured to generate first and second internal clock pulses from a rising edge of an external clock signal and to provide the first and second internal clock signals to the multiplexing address latch. The multiplexing address latch is configured to output a first address signal in response to the first internal clock pulse and a second address signal in response to the second internal clock pulse.Type: GrantFiled: February 27, 2017Date of Patent: December 29, 2020Assignee: SURECORE LIMITEDInventor: Stefan Cosemans
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Patent number: 10867666Abstract: There is provided a memory unit comprising an array of memory cells and a driver circuit configured to output an output address signal that addresses a portion/subset of the array of memory cells. The driver circuit comprises a logic gate that is configured to receive one or more input address signals and to provide an output address signal in dependence upon the one or more input address signals, and wherein the logic gate is configured to output a drive voltage provided by a first of the one or more input address signals as the output address signal when the output of the logic gate is true/high.Type: GrantFiled: June 2, 2017Date of Patent: December 15, 2020Assignee: SURECORE LIMITEDInventors: Stefan Cosemans, Bram Rooseleer
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Publication number: 20200327931Abstract: There is provided a memory unit comprising an array of memory cells and a driver circuit configured to output an output address signal that addresses a portion/subset of the array of memory cells. The driver circuit comprises a logic gate that is configured to receive one or more input address signals and to provide an output address signal in dependence upon the one or more input address signals, and wherein the logic gate is configured to output a drive voltage provided by a first of the one or more input address signals as the output address signal when the output of the logic gate is true/high.Type: ApplicationFiled: June 2, 2017Publication date: October 15, 2020Inventors: Stefan COSEMANS, Bram ROOSELEER
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Publication number: 20200327924Abstract: There is provided a method for accessing a memory cell of a plurality of memory cells that are part of a memory unit, the memory cells being grouped into a plurality of memory cell groups, wherein each memory cell group is associated with one or more local bit lines with each of the one or more local bit lines being operatively connected to a corresponding global bit line via a passgate comprising a PMOS transistor. The method comprises connecting each of the one or more local bit lines to the corresponding global bit line by decreasing a gate voltage that is applied to a gate of the corresponding PMOS transistor to a value that is sufficient to allow the PMOS transistor to conduct, wherein the value of the gate voltage that is sufficient to allow the PMOS transistor to conduct is either a positive or negative voltage.Type: ApplicationFiled: June 2, 2017Publication date: October 15, 2020Inventors: Stefan COSEMANS, Bram ROOSELEER
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Publication number: 20200203273Abstract: Integrated circuit comprising an interconnection system comprising at least one multilevel layer comprising first parallel electrically conductive lines, the multilevel layer comprising at least three levels forming a centerline level, an upper extension line level, and a lower extension line level the levels providing multilevel routing tracks in which the lines extend.Type: ApplicationFiled: December 19, 2019Publication date: June 25, 2020Inventors: Stefan Cosemans, Julien Ryckaert, Zsolt Tokei
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Patent number: 10593395Abstract: There is provided a multiple data rate memory configured to implement first and second memory accesses within a single cycle of an external clock signal. The memory comprises a plurality of memory cell groups, each memory cell group comprising a plurality of memory cells that are each operatively connected to at least one local bit line, the at least one local bit line of each memory cell group being connected to a local-to-global interface circuit. The local-to-global interface circuit is configured to control the state of at least one first global bit line in dependence upon the state of the at least one local bit line during the first memory access and to control the state of at least one second global bitline in dependence upon the state of the at least one local bit line during the second memory access.Type: GrantFiled: February 28, 2017Date of Patent: March 17, 2020Assignee: SURECORE LIMITEDInventors: Stefan Cosemans, Bram Rooseleer
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METHOD FOR MANUFACTURING A MAGNETIC TUNNEL JUNCTION DEVICE AND DEVICE MANUFACTURED USING SUCH METHOD
Publication number: 20190221608Abstract: A magnetic tunnel junction memory device is disclosed. In one aspect, the memory device comprises a substrate, a first memory element, and a second memory element, wherein the first memory element and the second memory element are formed of a stack comprising at least a first layer and a second layer, the first layer being arranged between the substrate and the second layer. The memory device further comprises a first selector device arranged to contact the first memory element, and a second selector device arranged to contact the second memory element, wherein the first selector device and the second selector device are arranged in or above the second layer. The first memory element and the second memory element are interconnected via the first layer, and are separated from each other by a trench formed in the second layer.Type: ApplicationFiled: December 28, 2018Publication date: July 18, 2019Inventors: Gouri Sankar Kar, Stefan Cosemans -
Publication number: 20190103155Abstract: There is provided a multiple data rate memory configured to implement first and second memory accesses within a single cycle of an external clock signal. The memory comprises a plurality of memory cell groups, each memory cell group comprising a plurality of memory cells that are each operatively connected to at least one local bit line, the at least one local bit line of each memory cell group being connected to a local-to-global interface circuit. The local-to-global interface circuit is configured to control the state of at least one first global bit line in dependence upon the state of the at least one local bit line during the first memory access and to control the state of at least one second global bitline in dependence upon the state of the at least one local bit line during the second memory access.Type: ApplicationFiled: February 28, 2017Publication date: April 4, 2019Inventors: Stefan COSEMANS, Bram ROOSELEER
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Publication number: 20190080735Abstract: There is provided a multiple data rate memory comprising a clock splitting circuit and a multiplexing address latch. The clock splitting circuit is configured to generate first and second internal clock pulses from a rising edge of an external clock signal and to provide the first and second internal clock signals to the multiplexing address latch. The multiplexing address latch is configured to output a first address signal in response to the first internal clock pulse and a second address signal in response to the second internal clock pulse.Type: ApplicationFiled: February 27, 2017Publication date: March 14, 2019Inventor: Stefan COSEMANS