Patents by Inventor Stefan Cosemans
Stefan Cosemans has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20190080735Abstract: There is provided a multiple data rate memory comprising a clock splitting circuit and a multiplexing address latch. The clock splitting circuit is configured to generate first and second internal clock pulses from a rising edge of an external clock signal and to provide the first and second internal clock signals to the multiplexing address latch. The multiplexing address latch is configured to output a first address signal in response to the first internal clock pulse and a second address signal in response to the second internal clock pulse.Type: ApplicationFiled: February 27, 2017Publication date: March 14, 2019Inventor: Stefan COSEMANS
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Patent number: 10102908Abstract: A microcomputer comprising a microprocessor unit and a first memory unit is disclosed. In one aspect, the microprocessor unit comprises at least one functional unit and at least one register. Further, the at least one register is a wide register comprising a plurality of second memory units which are capable to each contain one word, the wide register being adapted so that the second memory units are simultaneously accessible by the first memory unit, and at least part of the second memory units are separately accessible by the at least one functional unit. Further, the first memory unit is an embedded non-volatile memory unit.Type: GrantFiled: February 15, 2018Date of Patent: October 16, 2018Assignee: IMECInventors: Francky Catthoor, Komalan Manu Perumkunnil, Stefan Cosemans
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Patent number: 10043798Abstract: A semiconductor circuit comprises a Front End of Line (FEOL) comprising a plurality of transistors, each of which having a source region, a drain region and a gate region arranged between the source region and the drain region and comprising a gate electrode. The semiconductor circuit also comprises a buried interconnect that is arranged in the FEOL and electrically connected to the gate region from below through a bottom contact portion of the gate electrode. By using a buried interconnect the routing of the circuit may be facilitated.Type: GrantFiled: August 25, 2016Date of Patent: August 7, 2018Assignee: IMEC VZWInventors: Stefan Cosemans, Praveen Raghavan, Steven Demuynck, Julien Ryckaert
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Publication number: 20180174653Abstract: A microcomputer comprising a microprocessor unit and a first memory unit is disclosed. In one aspect, the microprocessor unit comprises at least one functional unit and at least one register. Further, the at least one register is a wide register comprising a plurality of second memory units which are capable to each contain one word, the wide register being adapted so that the second memory units are simultaneously accessible by the first memory unit, and at least part of the second memory units are separately accessible by the at least one functional unit. Further, the first memory unit is an embedded non-volatile memory unit.Type: ApplicationFiled: February 15, 2018Publication date: June 21, 2018Inventors: Francky Catthoor, Komalan Manu Perumkunnil, Stefan Cosemans
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Patent number: 9911504Abstract: A data storage cell for storing data is disclosed. In one aspect, the data storage cell comprises a first nano electromechanical switch comprising a first moveable beam fixed to a first anchor, a first control gate and a second control gate, a first output node against which the first moveable beam can be positioned. The data storage cell also comprises a second nano electromechanical switch comprising a second moveable beam fixed to a second anchor, a third control gate and a fourth control gate. The second moveable beam can be positioned against the first output node. Further, the first nano electromechanical switch and the second nano electromechanical switch are configured for selecting a first or a second state of the data storage cell and are configured for having their moveable beam complementary positioned to the first output node.Type: GrantFiled: December 2, 2014Date of Patent: March 6, 2018Assignee: IMEC vzwInventor: Stefan Cosemans
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Patent number: 9899086Abstract: A microcomputer comprising a microprocessor unit and a first memory unit is disclosed. In one aspect, the microprocessor unit comprises at least one functional unit and at least one register. Further, the at least one register is a wide register comprising a plurality of second memory units which are capable to each contain one word, the wide register being adapted so that the second memory units are simultaneously accessible by the first memory unit, and at least part of the second memory units are separately accessible by the at least one functional unit. Further, the first memory unit is an embedded non-volatile memory unit.Type: GrantFiled: January 24, 2014Date of Patent: February 20, 2018Assignee: IMECInventors: Francky Catthoor, Komalan Manu Perumkunnil, Stefan Cosemans
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Publication number: 20170062421Abstract: A semiconductor circuit comprises a Front End of Line (FEOL) comprising a plurality of transistors, each of which having a source region, a drain region and a gate region arranged between the source region and the drain region and comprising a gate electrode. The semiconductor circuit also comprises a buried interconnect that is arranged in the FEOL and electrically connected to the gate region from below through a bottom contact portion of the gate electrode. By using a buried interconnect the routing of the circuit may be facilitated.Type: ApplicationFiled: August 25, 2016Publication date: March 2, 2017Inventors: Stefan Cosemans, Praveen Raghavan, Steven Demuynck, Julien Ryckaert
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Patent number: 9278848Abstract: The disclosed technology relates generally to electromechanical devices, and relates more specifically to a nanoelectromechanical switch device and a method for manufacturing the same. In one aspect, an electromechanical device includes a first electrode stack and a second electrode stack, both electrode stacks extending in a vertical direction relative to a substrate surface and being spaced apart by a gap.Type: GrantFiled: December 18, 2013Date of Patent: March 8, 2016Assignees: IMEC, Katholieke Universiteit LeuvenInventors: Ann Witvrouw, Maliheh Ramezani, Stefan Cosemans
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Patent number: 9224448Abstract: A non-volatile memory arrangement comprising a plurality of cells is disclosed. In one aspect, each cell comprises a memory element and a read selector in series. Further, the memory element is a nano-electro-mechanical switch comprising an anchor, a beam fixed to the anchor, a first and second control gate, for controlling the position of the beam, a first output node against which the beam can be positioned. The cell also comprises a read selector comprising a first selector terminal, a second selector terminal, the first selector terminal connected to the first output node. The first respectively second control gates of switches of a same word are connected together by a first respectively second write word line serving as control gate.Type: GrantFiled: December 2, 2014Date of Patent: December 29, 2015Assignees: IMEC vzw, Katholieke Universiteit LeuvenInventors: Stefan Cosemans, Ann Witvrouw, Maliheh Ramezani
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Patent number: 9159415Abstract: The disclosed technology relates to a non-volatile resistive memory device and a method of using the same. In one aspect, the memory device comprises a plurality of memory cells interconnected by a plurality of bit lines, a plurality of word lines, a plurality of source lines and a plurality of form lines. The memory device further comprises a memory controller connected to and configured to apply voltages to the bit lines, the word lines, the source lines and the form lines. In addition, each of the memory cells comprises a cell selecting transistor and a resistive memory element serially connected to a drain-source path of the cell selecting transistor. Furthermore, each of the memory cells comprises a boosting capacitor configured to provide a boosting a voltage to an internal node formed at a connection point between the resistive memory element and the cell selecting transistor.Type: GrantFiled: September 27, 2013Date of Patent: October 13, 2015Assignee: IMECInventor: Stefan Cosemans
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Publication number: 20150179246Abstract: A non-volatile memory arrangement comprising a plurality of cells is disclosed. In one aspect, each cell comprises a memory element and a read selector in series. Further, the memory element is a nano-electro-mechanical switch comprising an anchor, a beam fixed to the anchor, a first and second control gate, for controlling the position of the beam, a first output node against which the beam can be positioned. The cell also comprises a read selector comprising a first selector terminal, a second selector terminal, the first selector terminal connected to the first output node. The first respectively second control gates of switches of a same word are connected together by a first respectively second write word line serving as control gate.Type: ApplicationFiled: December 2, 2014Publication date: June 25, 2015Inventors: Stefan Cosemans, Ann Witvrouw, Maliheh Ramezani
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Publication number: 20150179278Abstract: A data storage cell for storing data is disclosed. In one aspect, the data storage cell comprises a first nano electromechanical switch comprising a first moveable beam fixed to a first anchor, a first control gate and a second control gate, a first output node against which the first moveable beam can be positioned. The data storage cell also comprises a second nano electromechanical switch comprising a second moveable beam fixed to a second anchor, a third control gate and a fourth control gate. The second moveable beam can be positioned against the first output node. Further, the first nano electromechanical switch and the second nano electromechanical switch are configured for selecting a first or a second state of the data storage cell and are configured for having their moveable beam complementary positioned to the first output node.Type: ApplicationFiled: December 2, 2014Publication date: June 25, 2015Inventor: Stefan Cosemans
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Patent number: 8958238Abstract: A memory device having complementary global and local bit-lines, the complementary local bit-lines being connectable to the complementary global bit-lines by means of a local write receiver which is configured for creating a full voltage swing on the complementary local bit lines from a reduced voltage swing on the complementary global bit lines. The local write receiver comprises a connection mechanism for connecting the local to the global bit-lines and a pair of cross-coupled inverters directly connected to the complementary local bit lines for converting the reduced voltage swing to the full voltage swing on the complementary local bit lines.Type: GrantFiled: August 30, 2013Date of Patent: February 17, 2015Assignees: Stichting IMEC Nederland, Kathoieke Universiteit LeuvenInventors: Vibhu Sharma, Stefan Cosemans, Wim Dehaene, Francky Catthoor, Maryam Ashouei, Jos Huisken
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Publication number: 20140289457Abstract: A microcomputer comprising a microprocessor unit and a first memory unit is disclosed. In one aspect, the microprocessor unit comprises at least one functional unit and at least one register. Further, the at least one register is a wide register comprising a plurality of second memory units which are capable to each contain one word, the wide register being adapted so that the second memory units are simultaneously accessible by the first memory unit, and at least part of the second memory units are separately accessible by the at least one functional unit. Further, the first memory unit is an embedded non-volatile memory unit.Type: ApplicationFiled: January 24, 2014Publication date: September 25, 2014Applicant: IMECInventors: Francky Catthoor, Komalan Manu Perumkunnil, Stefan Cosemans
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Publication number: 20140225167Abstract: The disclosed technology relates generally to electromechanical devices, and relates more specifically to a nanoelectromechanical switch device and a method for manufacturing the same. In one aspect, an electromechanical device includes a first electrode stack and a second electrode stack, both electrode stacks extending in a vertical direction relative to a substrate surface and being spaced apart by a gap.Type: ApplicationFiled: December 18, 2013Publication date: August 14, 2014Applicants: Katholieke Universiteit Leuven, IMECInventors: Ann Witvrouw, Maliheh Ramezani, Stefan Cosemans
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Publication number: 20140092670Abstract: The disclosed technology relates to a non-volatile resistive memory device and a method of using the same. In one aspect, the memory device comprises a plurality of memory cells interconnected by a plurality of bit lines, a plurality of word lines, a plurality of source lines and a plurality of form lines. The memory device further comprises a memory controller connected to and configured to apply voltages to the bit lines, the word lines, the source lines and the form lines. In addition, each of the memory cells comprises a cell selecting transistor and a resistive memory element serially connected to a drain-source path of the cell selecting transistor. Furthermore, each of the memory cells comprises a boosting capacitor configured to provide a boosting a voltage to an internal node formed at a connection point between the resistive memory element and the cell selecting transistor.Type: ApplicationFiled: September 27, 2013Publication date: April 3, 2014Applicant: IMECInventor: Stefan Cosemans
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Publication number: 20140071737Abstract: A memory device having complementary global and local bit-lines, the complementary local bit-lines being connectable to the complementary global bit-lines by means of a local write receiver which is configured for creating a full voltage swing on the complementary local bit lines from a reduced voltage swing on the complementary global bit lines. The local write receiver comprises a connection mechanism for connecting the local to the global bit-lines and a pair of cross-coupled inverters directly connected to the complementary local bit lines for converting the reduced voltage swing to the full voltage swing on the complementary local bit lines.Type: ApplicationFiled: August 30, 2013Publication date: March 13, 2014Applicants: Katholieke Universiteit Leuven, Stichting IMEC NederlandInventors: Vibhu Sharma, Stefan Cosemans, Wim Dehaene, Francky Catthoor, Maryam Ashouei, Jos Huisken
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Patent number: 8625187Abstract: A DND chip is disclosed. In one aspect, the chip includes a 2D DND array of DND elements logically arranged in rows and columns, and a DND driver architecture for actuating the DND elements. The DND driver has a set of first drive lines along the rows and a set of second drive lines along the columns, a set of first line drivers for each biasing one line from the set of first drive lines and a set of second line drivers for each biasing a line from the set of second drive lines. A plurality of second line drivers are spatially grouped together to serve a block of DND elements, and that plurality of second line drivers are spatially covered substantially completely by at least some DND elements of the block of DND elements. A holographic visualization system including the DND chip is provided.Type: GrantFiled: November 16, 2011Date of Patent: January 7, 2014Assignee: IMECInventors: Geert Van Der Plas, Stefan Cosemans
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Patent number: 8462572Abstract: An ultra low power sense amplifier circuit for amplifying a low swing input signal to a full swing output signal is disclosed. In one aspect, the amplifier circuit includes a first amplifier stage for pre-amplifying the input signal to an intermediate signal on its internal nodes, a second amplifier stage for amplifying the intermediate signal to the output signal, and a control circuit for sequentially activating the first and second amplifier. The first amplifier has a capacitor for limiting energy consumption and two upsized PMOS transistors without NMOS transistors.Type: GrantFiled: September 13, 2011Date of Patent: June 11, 2013Assignees: Stichting IMEC Nederland, Katholieke Universiteit LeuvenInventors: Vibhu Sharma, Stefan Cosemans, Wim Dehaene, Francky Catthoor, Maryam Ashouei, Jos Huisken
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Publication number: 20120127559Abstract: A DND chip is disclosed. In one aspect, the chip includes a 2D DND array of DND elements logically arranged in rows and columns, and a DND driver architecture for actuating the DND elements. The DND driver has a set of first drive lines along the rows and a set of second drive lines along the columns, a set of first line drivers for each biasing one line from the set of first drive lines and a set of second line drivers for each biasing a line from the set of second drive lines. A plurality of second line drivers are spatially grouped together to serve a block of DND elements, and that plurality of second line drivers are spatially covered substantially completely by at least some DND elements of the block of DND elements. A holographic visualization system including the DND chip is provided.Type: ApplicationFiled: November 16, 2011Publication date: May 24, 2012Applicant: IMECInventors: Geert VAN DER PLAS, Stefan Cosemans