Abstract: Example methods, systems, and apparatus are described herein. An example gas block is described for an automatic firearm, which has a gas cylinder that can be connected in a fluid-tight manner to a hole in the gun barrel via a gas channel, characterized by a control element that can be switched between at least two positions and is designed to open the gas channel in the first position, in which the fluid-tight connection is obtained, and to close the gas channel in the second position, in which the fluid-tight connection is interrupted. The disclosure also relates to a control element, a gun barrel equipped with the gas block, and an automatic firearm equipped with the gas block.

Abstract: A glitch detector includes a metastability detector circuit, a reference storage circuit, and a pattern comparison circuit. The metastability detector circuit is configured to generate state signals at each cycle of the clock signal. The reference storage circuit is configured to store a logic state of each state signal based on a delayed version of the clock signal, and generate reference signals. A logic state of each reference signal is equal to a logic state of a corresponding state signal generated during a previous cycle of the clock signal. The pattern comparison circuit is configured to receive the state signals generated during a current cycle of the clock signal, the reference signals, and first and second values, and generate clock and voltage glitch signals based on first and second patterns that are associated with the state signals generated during the current cycle and the reference signals, respectively.

Abstract: A glitch detector includes a metastability detector circuit, a reference storage circuit, and a pattern comparison circuit. The metastability detector circuit is configured to generate state signals at each cycle of the clock signal. The reference storage circuit is configured to store a logic state of each state signal based on a delayed version of the clock signal, and generate reference signals. A logic state of each reference signal is equal to a logic state of a corresponding state signal generated during a previous cycle of the clock signal. The pattern comparison circuit is configured to receive the state signals generated during a current cycle of the clock signal, the reference signals, and first and second values, and generate clock and voltage glitch signals based on first and second patterns that are associated with the state signals generated during the current cycle and the reference signals, respectively.

Abstract: A glitch detector includes a metastability detector circuit, a reference storage circuit, and a pattern comparison circuit. The metastability detector circuit is configured to generate state signals at each cycle of the clock signal. The reference storage circuit is configured to store a logic state of each state signal based on a delayed version of the clock signal, and generate reference signals. A logic state of each reference signal is equal to a logic state of a corresponding state signal generated during a previous cycle of the clock signal. The pattern comparison circuit is configured to receive the state signals generated during a current cycle of the clock signal, the reference signals, and first and second values, and generate clock and voltage glitch signals based on first and second patterns that are associated with the state signals generated during the current cycle and the reference signals, respectively.

Abstract: A glitch detector includes a metastability detector circuit, a reference storage circuit, and a pattern comparison circuit. The metastability detector circuit is configured to generate state signals at each cycle of the clock signal. The reference storage circuit is configured to store a logic state of each state signal based on a delayed version of the clock signal, and generate reference signals. A logic state of each reference signal is equal to a logic state of a corresponding state signal generated during a previous cycle of the clock signal. The pattern comparison circuit is configured to receive the state signals generated during a current cycle of the clock signal, the reference signals, and first and second values, and generate clock and voltage glitch signals based on first and second patterns that are associated with the state signals generated during the current cycle and the reference signals, respectively.

Abstract: A system for securing a secret word during a read of the secret word from a read-only memory (ROM) is disclosed. The system includes a memory controller coupled to the ROM and a random number generator coupled to the memory controller. The random number generator is configured to generate a random number. The system further includes a number shuffler coupled to the random number generator and the memory controller. The number shuffler is configured to generate a bit read order based on the random number and the memory controller is configured to read bits of the secret word from the ROM according to the bit read order.

Abstract: A circuit includes a one-time programmable (OTP) storage element configured to store a first logic value, an access delay timer configured to initiate a timer in response to a reset event with a timer value, and an access control circuit coupled to the access delay timer and the OTP storage element. The access control circuit is configured to count a number of access requests to the OTP storage element granted by the access control circuit and to store the number of granted access requests to the OTP storage element as a count value. The access control circuit is also configured to grant access to the OTP storage element in response to an access request only when the timer has expired and the count value is less than a predetermined count threshold.

Abstract: A fully digital integrated circuit apparatus (200) and method (300) are provided for generating a test mode enable signal with a digital non-resettable state retention storage circuit (210) connected to store an authentication control pattern for authorizing test mode access to a secure circuit, a digital safety interlock gate circuit (220) connected to store a safety interlock gate setting that may be accessed independently from a test mode enable signal, and combinatorial logic circuitry (205) for generating the test mode enable signal only when the interlock safety gate setting is set to a first value and the digital non-resettable state retention storage circuit stores the authentication control code.

Abstract: A system for securing a secret word during a read of the secret word from a read-only memory (ROM) is disclosed. The system includes a memory controller coupled to the ROM and a random number generator coupled to the memory controller. The random number generator is configured to generate a random number. The system further includes a number shuffler coupled to the random number generator and the memory controller. The number shuffler is configured to generate a bit read order based on the random number and the memory controller is configured to read bits of the secret word from the ROM according to the bit read order.

Abstract: Example apparatus and method are disclosed for a unitary firearm housing for an automatic firearm, comprising a barrel receptacle configured as an internal component of the unitary firearm housing.

Abstract: A clock glitch alerting circuit is configured to detect a glitch in an input clock signal, and activate and provide an alert signal to a security controller when the glitch is detected. The clock glitch alerting circuit is further configured to delay the input clock signal based on multiple selection signals, and provide one of a delayed clock output signal and a filtered clock output signal to the security controller based on the alert signal. The clock glitch alerting circuit is further configured to generate and provide a count value to the security controller that indicates a time duration available by the security controller to execute a security critical operation after receiving the activated alert signal.

Abstract: Example apparatus are disclosed for an adapter to attach at least one device to a self-loading firearm, the adapter comprising a barrel-side section and a receiver-side section adjacent the barrel-side section, wherein the barrel-side section and the receiver-side section extend in a longitudinal direction of the firearm, wherein one of the barrel-side section and the receiver-side section is securable to a retention device on a firearm barrel or a firearm receiver, and wherein the other of the barrel-side section and the receiver-side section can be moveably supported on the firearm receiver or the firearm barrel by a guide that allows for longitudinal movement of the receiver-side section or the barrel-side section with respect to the firearm.

Abstract: A fully digital integrated circuit apparatus (200) and method (300) are provided for generating a test mode enable signal with a digital non-resettable state retention storage circuit (210) connected to store an authentication control pattern for authorizing test mode access to a secure circuit, a digital safety interlock gate circuit (220) connected to store a safety interlock gate setting that may be accessed independently from a test mode enable signal, and combinatorial logic circuitry (205) for generating the test mode enable signal only when the interlock safety gate setting is set to a first value and the digital non-resettable state retention storage circuit stores the authentication control code.

Abstract: Example apparatus are disclosed for a gas feed for an automatic firearm, the gas feed comprising a mounting portion to fasten the gas feed on a firearm barrel, the gas feed comprising a gas cylinder connectable to a barrel bore inside the firearm barrel via a gas channel, a gas piston disposed inside the gas cylinder to drive a gas operated reloading mechanism, wherein the gas piston is displaceable in a longitudinal direction with respect to the firearm, and a closure element that can be detachably coupled to an end of the gas cylinder adjacent a stock of the firearm, wherein the closure element comprises a passage through which a gas piston can be disposed.

Abstract: A method, system, and apparatus are provided for preventing glitch attacks by using a glitch processing hardware unit (1) to deactivate a glitch filter connected between the monitored line and a reset processing unit in response to detecting a voltage glitch on a monitored line during a specified security system sequence and (2) to automatically drive a requested reaction in response to the voltage glitch by driving one of a plurality of configurable reactions comprising a device reset reaction and a process restart request, thereby preventing the voltage glitch from maliciously influencing the specified security system sequence.

Abstract: A device is disclosed. The device includes a read-only memory (ROM), a random key generator, a lifecycle controller, an access port and a processor. The processor is configured, based on a lifecycle status, to cause the random key generator to generate a secret key and store the secret key in the ROM. The lifecycle controller is configured to disable an external access via the access port until the secret key is stored in the ROM.

Abstract: A system for securing a secret word during a read of the secret word from a read-only memory (ROM) is disclosed. The system includes a memory controller coupled to the ROM and a random number generator coupled to the memory controller. The random number generator is configured to generate a random number. The system further includes a number shuffler coupled to the random number generator and the memory controller. The number shuffler is configured to generate a bit read order based on the random number and the memory controller is configured to read bits of the secret word from the ROM according to the bit read order.

Abstract: Various embodiments relate to a circuit, including: a first secure circuit configured to receive an input and to produce a first output; a first delay circuit configured to receive the first output and to produce a first delayed output delayed by a time N; a second delay circuit configured to receive the input and to produce a delayed input delayed by a time N; a second secure circuit configured to receive the delayed input and to produce a second delayed output; and a comparator configured to compare the first delayed output to the second delayed output and to produce a result, wherein the result is one of the first delayed output or second delayed output when the first delayed output matches the second delayed output and the result is an error value when the first delayed output does not match the second delayed output.

Abstract: An integrated circuit includes a security module with multiple stages arranged in a pipeline, with each stage executing a different operation for accessing stored lifecycle (LC) information. For each portion of LC being accessed, each stage performs N iterations of its corresponding operation, whereby N is an integer greater than two, and crosschecks the results of successive iterations to ensure that the results of the operation are consistent. In addition, the stages of the security module are overlapping, such that different stages can perform different iterations concurrently. These concurrent operations at different stages are organized such that they may also be crosschecked and thereby confirm “offset” results between the stages.

Abstract: A method, system, and apparatus are provided for preventing glitch attacks by using a glitch processing hardware unit (1) to deactivate a glitch filter connected between the monitored line and a reset processing unit in response to detecting a voltage glitch on a monitored line during a specified security system sequence and (2) to automatically drive a requested reaction in response to the voltage glitch by driving one of a plurality of configurable reactions comprising a device reset reaction and a process restart request, thereby preventing the voltage glitch from maliciously influencing the specified security system sequence.