Patents by Inventor Stefan Flachowsky

Stefan Flachowsky has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10340380
    Abstract: A semiconductor device includes a plurality of spaced apart fins, a dielectric material layer positioned between each of the plurality of spaced apart fins, and a common gate structure positioned above the dielectric material layer and extending across the fins. A continuous merged semiconductor material region is positioned on each of the fins and above the dielectric material layer, is laterally spaced apart from the common gate structure, extends between and physically contacts the fins, has a first sidewall surface that faces toward the common gate structure, and has a second sidewall surface that is opposite of the first sidewall surface and faces away from the common gate structure. A stress-inducing material is positioned in a space defined by at least the first sidewall surface, opposing sidewall surfaces of an adjacent pair of fins, and an upper surface of the dielectric material layer.
    Type: Grant
    Filed: May 23, 2016
    Date of Patent: July 2, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Stefan Flachowsky, Jan Hoentschel, Ralf Richter, Peter Javorka
  • Patent number: 10084057
    Abstract: The present disclosure provides in one aspect a semiconductor device including a substrate structure comprising an active semiconductor material formed over a base substrate and a buried insulating material formed between the active semiconductor material and the base substrate, a ferroelectric gate structure disposed over the active semiconductor material in an active region of the substrate structure, the ferroelectric gate structure comprising a gate electrode and a ferroelectric material layer, and a contact region formed in the base substrate under the ferroelectric gate structure.
    Type: Grant
    Filed: August 16, 2016
    Date of Patent: September 25, 2018
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Sven Beyer, Martin Trentzsch, Stefan Flachowsky, Axel Henke
  • Patent number: 10056376
    Abstract: A semiconductor device includes a semiconductor substrate and a fin positioned above the semiconductor substrate, wherein the fin includes a semiconductor material. Additionally, a ferroelectric high-k spacer covers sidewall surfaces of the fin and a non-ferroelectric high-k material layer covers the ferroelectric high-k spacer and the fin, wherein a portion of the non-ferroelectric high-k material layer is positioned on and in direct contact with the semiconductor material at the upper surface of the fin.
    Type: Grant
    Filed: August 16, 2016
    Date of Patent: August 21, 2018
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Stefan Flachowsky, Ralf Illgen, Jan Hoentschel
  • Publication number: 20180151577
    Abstract: An illustrative device disclosed herein includes a semiconductor substrate. The substrate includes a source region, a drain region and a channel region. The channel region is arranged between the source region and the drain region. A gate insulation layer is provided over the channel region. A floating gate electrode is provided over the gate insulation layer. A layer of a ferroelectric material is provided over the floating gate electrode. A top electrode is provided over the layer of ferroelectric material. A projected area of the top electrode onto a plane that is perpendicular to a thickness direction of the semiconductor substrate is smaller than a projected area of the floating gate electrode onto the plane.
    Type: Application
    Filed: January 8, 2018
    Publication date: May 31, 2018
    Applicants: Fraunhofer-Gesellschaft zur Foerderung der angewan dten Forschung e.V., NaMLab gGmbH
    Inventors: Johannes Mueller, Stefan Mueller, Stefan Flachowsky
  • Patent number: 9966466
    Abstract: A semiconductor-on-insulator wafer includes a support substrate, an electrically insulating layer over the support substrate and a semiconductor layer over the electrically insulating layer. A semiconductor structure includes a transistor. The transistor includes an electrically insulating layer including a piezoelectric material over a support substrate, a semiconductor layer over the electrically insulating layer, a source region, a channel region and a drain region in the semiconductor layer, a gate structure over the channel region, a first electrode and a second electrode. The first electrode and the second electrode are provided at laterally opposite sides of the electrically insulating layer. The first and second electrodes are electrically insulated from the semiconductor layer and configured for applying a voltage to the piezoelectric material of the electrically insulating layer. The piezoelectric material creates a strain at least in the channel region in response to the voltage applied thereto.
    Type: Grant
    Filed: August 8, 2016
    Date of Patent: May 8, 2018
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Stefan Flachowsky, Ralf Illgen
  • Publication number: 20180053832
    Abstract: The present disclosure provides in one aspect a semiconductor device including a substrate structure comprising an active semiconductor material formed over a base substrate and a buried insulating material formed between the active semiconductor material and the base substrate, a ferroelectric gate structure disposed over the active semiconductor material in an active region of the substrate structure, the ferroelectric gate structure comprising a gate electrode and a ferroelectric material layer, and a contact region formed in the base substrate under the ferroelectric gate structure.
    Type: Application
    Filed: August 16, 2016
    Publication date: February 22, 2018
    Inventors: Sven Beyer, Martin Trentzsch, Stefan Flachowsky, Axel Henke
  • Patent number: 9899417
    Abstract: A semiconductor structure includes a semiconductor substrate, a layer of electrically insulating material above the semiconductor substrate, and a layer of semiconductor material above the layer of electrically insulating material. A first transistor includes a first source region, a first drain region, and a first channel region formed in the semiconductor substrate, a first gate insulation layer positioned above the first channel region, and an electrically conductive first gate electrode, wherein the first gate insulation layer includes a first portion of the electrically insulating material. A second transistor includes a second source region, a second drain region, and a second channel region formed in the layer of semiconductor material, a second gate insulation layer positioned above the second channel region, and an electrically conductive second gate electrode, wherein a second portion of the layer of electrically insulating material is positioned below the second channel region.
    Type: Grant
    Filed: March 23, 2017
    Date of Patent: February 20, 2018
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Stefan Flachowsky, Ralf Illgen
  • Publication number: 20180040731
    Abstract: A semiconductor-on-insulator wafer includes a support substrate, an electrically insulating layer over the support substrate and a semiconductor layer over the electrically insulating layer. A semiconductor structure includes a transistor. The transistor includes an electrically insulating layer including a piezoelectric material over a support substrate, a semiconductor layer over the electrically insulating layer, a source region, a channel region and a drain region in the semiconductor layer, a gate structure over the channel region, a first electrode and a second electrode. The first electrode and the second electrode are provided at laterally opposite sides of the electrically insulating layer. The first and second electrodes are electrically insulated from the semiconductor layer and configured for applying a voltage to the piezoelectric material of the electrically insulating layer. The piezoelectric material creates a strain at least in the channel region in response to the voltage applied thereto.
    Type: Application
    Filed: August 8, 2016
    Publication date: February 8, 2018
    Inventors: Stefan Flachowsky, Ralf Illgen
  • Patent number: 9865608
    Abstract: A method disclosed herein includes providing a semiconductor structure, the semiconductor structure comprising a semiconductor substrate and a gate stack, the gate stack comprising a gate insulation material over the substrate, a floating gate electrode material over the gate insulation material, a ferroelectric transistor dielectric over the floating gate electrode material and a top electrode material over the ferroelectric transistor dielectric, performing a first patterning process to remove portions of the top electrode material and the ferroelectric transistor dielectric and performing a second patterning process after the first patterning process to remove portions of the floating gate electrode material and the gate insulation material, wherein a projected area of an upper portion of the gate structure onto a plane that is perpendicular to a thickness direction of the substrate is smaller than a projected area of the lower portion of the gate structure onto the plane.
    Type: Grant
    Filed: May 23, 2016
    Date of Patent: January 9, 2018
    Assignees: GLOBALFOUNDRIES Inc., Fraunhofer Gesellschaft zur Foerderung der angewandted Forschung e.V., NaMLab gGmbH
    Inventors: Johannes Mueller, Stefan Mueller, Stefan Flachowsky
  • Publication number: 20170338350
    Abstract: The present disclosure provides a semiconductor device including a substrate, a gate structure formed over the substrate, the gate structure including a first ferroelectric material having a first remanent polarization and a second ferroelectric material having a second remanent polarization, the first remanent polarization being smaller than the second remanent polarization, and source and drain regions formed in the substrate, the source and drain regions being laterally separated by a channel region extending along a length direction below the gate structure, wherein the first ferroelectric material and the second ferroelectric material are stacked in a plane parallel to an upper surface of the substrate.
    Type: Application
    Filed: August 11, 2016
    Publication date: November 23, 2017
    Inventors: Stefan Flachowsky, Ralf Illgen
  • Publication number: 20170200743
    Abstract: A semiconductor structure includes a semiconductor substrate, a layer of electrically insulating material above the semiconductor substrate, and a layer of semiconductor material above the layer of electrically insulating material. A first transistor includes a first source region, a first drain region, and a first channel region formed in the semiconductor substrate, a first gate insulation layer positioned above the first channel region, and an electrically conductive first gate electrode, wherein the first gate insulation layer includes a first portion of the electrically insulating material. A second transistor includes a second source region, a second drain region, and a second channel region formed in the layer of semiconductor material, a second gate insulation layer positioned above the second channel region, and an electrically conductive second gate electrode, wherein a second portion of the layer of electrically insulating material is positioned below the second channel region.
    Type: Application
    Filed: March 23, 2017
    Publication date: July 13, 2017
    Inventors: Stefan Flachowsky, Ralf Illgen
  • Patent number: 9685457
    Abstract: A method includes providing a semiconductor-on-insulator structure including a semiconductor substrate, a layer of electrically insulating material over the semiconductor substrate and a layer of semiconductor material over the layer of electrically insulating material. A first transistor is formed. The formation of the first transistor includes forming a dummy gate structure over the layer of semiconductor material, forming a source region of the first transistor and a drain region of the first transistor in portions of the semiconductor substrate adjacent the dummy gate structure, forming an electrically insulating structure annularly enclosing the dummy gate structure and performing a replacement gate process. The replacement gate process includes removing the dummy gate structure and a portion of the layer of semiconductor material below the dummy gate structure, wherein a recess is formed in the electrically insulating structure. The recess is filled with an electrically conductive material.
    Type: Grant
    Filed: July 22, 2015
    Date of Patent: June 20, 2017
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Stefan Flachowsky, Ralf Illgen
  • Patent number: 9583240
    Abstract: The present disclosure relates to a semiconductor structure comprising a positive temperature coefficient thermistor and a negative temperature coefficient thermistor, connected to each other in parallel by means of connecting elements which are configured such that the resistance resulting from the parallel connection is substantially stable in a predetermined temperature range, and to a corresponding manufacturing method.
    Type: Grant
    Filed: August 26, 2014
    Date of Patent: February 28, 2017
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Stefan Flachowsky, Ralf Illgen, Jan Hoentschel
  • Publication number: 20170025442
    Abstract: A method includes providing a semiconductor-on-insulator structure including a semiconductor substrate, a layer of electrically insulating material over the semiconductor substrate and a layer of semiconductor material over the layer of electrically insulating material. A first transistor is formed. The formation of the first transistor includes forming a dummy gate structure over the layer of semiconductor material, forming a source region of the first transistor and a drain region of the first transistor in portions of the semiconductor substrate adjacent the dummy gate structure, forming an electrically insulating structure annularly enclosing the dummy gate structure and performing a replacement gate process. The replacement gate process includes removing the dummy gate structure and a portion of the layer of semiconductor material below the dummy gate structure, wherein a recess is formed in the electrically insulating structure. The recess is filled with an electrically conductive material.
    Type: Application
    Filed: July 22, 2015
    Publication date: January 26, 2017
    Inventors: Stefan Flachowsky, Ralf Illgen
  • Publication number: 20160358915
    Abstract: A semiconductor device includes a semiconductor substrate and a fin positioned above the semiconductor substrate, wherein the fin includes a semiconductor material. Additionally, a ferroelectric high-k spacer covers sidewall surfaces of the fin and a non-ferroelectric high-k material layer covers the ferroelectric high-k spacer and the fin, wherein a portion of the non-ferroelectric high-k material layer is positioned on and in direct contact with the semiconductor material at the upper surface of the fin.
    Type: Application
    Filed: August 16, 2016
    Publication date: December 8, 2016
    Inventors: Stefan Flachowsky, Ralf Illgen, Jan Hoentschel
  • Patent number: 9515155
    Abstract: E-fuses are used in integrated circuits in order to permit real-time dynamic reprogramming of the circuit after manufacturing. An e-fuse is hereby proposed wherein the metal element adapted to be blown upon passage of a current is not comprised of a silicide layer but is rather a metal layer above which a semiconductor layer is formed. A dielectric layer is then formed on the semiconductor layer, in order to prevent metal silicide from forming over the metal layer. The process of manufacturing the e-fuse can be easily integrated in an HKMG manufacturing flow. In particular, fully silicided metal gates may be manufactured in conjunction with the e-fuse, without jeopardizing the correct functioning of the e-fuse.
    Type: Grant
    Filed: December 20, 2013
    Date of Patent: December 6, 2016
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Roman Boschke, Stefan Flachowsky, Maciej Wiatr, Christian Schippel
  • Patent number: 9490344
    Abstract: Disclosed herein are various semiconductor devices with dual metal silicide regions and to various methods of making such devices. One illustrative method disclosed herein includes the steps of forming an upper portion of a source/drain region that is positioned above a surface of a semiconducting substrate, wherein the upper portion of the source/drain region has an upper surface that is positioned above the surface of the substrate by a distance that is at least equal to a target thickness of a metal silicide region to be formed in the upper portion of the source/drain region and forming the metal silicide region in the upper portion of the source/drain region.
    Type: Grant
    Filed: January 9, 2012
    Date of Patent: November 8, 2016
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Stefan Flachowsky, Jan Hoentschel, Thilo Scheiper
  • Patent number: 9490361
    Abstract: Lithographic limitations on gate and induced channel length in MOSFETS are avoided by forming non-planar MOSFETS in a cavity extending into a semiconductor substrate. The gate insulator and channel region lie proximate a cavity sidewall having angle ? preferably about ?90 degrees with respect to the semiconductor surface. The channel length depends on the bottom depth of the cavity and the depth from the surface of a source or drain region adjacent the cavity. The corresponding drain or source lies at the cavity bottom. The cavity sidewall extends therebetween. Neither depth is lithographic dependent. Very short channels can be consistently formed, providing improved performance and manufacturing yield. Source, drain and gate connections are brought to the same surface so that complex circuits can be readily constructed. The source and drain regions are preferably formed epitaxially and strain inducing materials can be used therein to improve channel carrier mobility.
    Type: Grant
    Filed: February 27, 2014
    Date of Patent: November 8, 2016
    Assignee: GLOBALFOUNDRIES, INC.
    Inventors: Stefan Flachowsky, Thilo Scheiper
  • Patent number: 9484407
    Abstract: A semiconductor device is provided including a semiconductor substrate and a nanowire formed over the semiconductor substrate and wherein the nanowire includes a first layer exhibiting tensile stress and a second layer exhibiting compressive stress.
    Type: Grant
    Filed: August 27, 2014
    Date of Patent: November 1, 2016
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Tim Baldauf, Stefan Flachowsky
  • Publication number: 20160315162
    Abstract: A semiconductor device structure includes an active region positioned in a semiconductor substrate and a gate structure of a transistor positioned above the active region. The gate structure includes a gate insulating layer, a gate metal layer positioned above the gate insulating layer and a trimmed gate electrode material layer positioned above the gate metal layer. A length of at least a portion of the trimmed gate electrode material layer in a gate length direction of the transistor is less than a length of at least the gate metal layer in the gate length direction.
    Type: Application
    Filed: July 5, 2016
    Publication date: October 27, 2016
    Inventors: Ralf Richter, Peter Javorka, Jan Hoentschel, Stefan Flachowsky