Abstract: In one example, a method disclosed herein includes the steps of forming a gate structure for a first transistor and a second transistor above a semiconducting substrate, forming a liner layer above the gate structures and performing a plurality of extension ion implant processes through the liner layer to form extension implant regions in the substrate for the first transistor and the second transistor. The method further includes forming a first sidewall spacer proximate the gate structure for the first transistor and a patterned hard mask layer positioned above the second transistor, performing at least one etching process to remove the first sidewall spacer, the patterned hard mask layer and the liner layer, forming a second sidewall spacer proximate both of the gate structures and performing a plurality of source/drain ion implant processes to form deep source/drain implant regions in the substrate for the first transistor and the second transistor.

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In an exemplary embodiment, an integrated circuit includes a semiconductor substrate doped with a first conductivity-determining impurity. The semiconductor substrate has formed therein a first well doped with a second conductivity-determining impurity that is different from the first conductivity-determining impurity, a second well, formed within the first well, and doped with the first conductivity-determining impurity, and a third well spaced apart from the first and second wells and doped with the second conductivity-determining impurity. The integrated circuit further includes a floating gate structure formed over the semiconductor substrate.

Abstract: When forming semiconductor devices comprising high performance or low-power field effect transistors, the threshold voltage of the transistors is adjusted by the halo implantation and the source and drain regions are defined by a single implantation step. Thus, the number of process steps is reduced, whereas the electrical characteristics, such as leakage level, and performance of the transistors are maintained compared to conventional transistors.

Abstract: When forming sophisticated SOI devices, a substrate diode and a film diode are formed by using one and the same implantation mask for determining the well dopant concentration in the corresponding well regions. Consequently, during the further processing, the well dopant concentration of any transistor elements may be achieved independently from the well regions of the diode in the semiconductor layer.

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided herein. In an embodiment of a method for fabricating integrated circuits, a P-type gate electrode structure and an N-type gate electrode structure are formed overlying a semiconductor substrate. The gate electrode structures each include a gate electrode that overlies a gate dielectric layer and a nitride cap that overlies the gate electrode. Conductivity determining ions are implanted into the semiconductor substrate using the P-type gate electrode structure and the N-type gate electrode structure as masks to form a source region and a drain region for the P-type gate electrode structure and the N-type gate electrode structure. The nitride cap remains overlying the N-type gate electrode structure during implantation of the conductivity determining ions into the semiconductor substrate to form the source region and the drain region for the N-type gate electrode structure.

Abstract: A known problem when manufacturing transistors is the stress undesirably introduced by the spacers into the transistor channel region. In order to solve this problem, the present invention proposes an ion implantation aimed at relaxing the stress of the spacer materials. The relax implantation is performed after the spacer has been completely formed. The relax implantation may be performed after a silicidation process or after an implantation step in the source and drain regions followed by an activation annealing and before performing the silicidation process.

Abstract: E-fuses are used in integrated circuits in order to permit real-time dynamic reprogramming of the circuit after manufacturing. An e-fuse is hereby proposed wherein the metal element adapted to be blown upon passage of a current is not comprised of a silicide layer but is rather a metal layer above which a semiconductor layer is formed. A dielectric layer is then formed on the semiconductor layer, in order to prevent metal silicide from forming over the metal layer. The process of manufacturing the e-fuse can be easily integrated in an HKMG manufacturing flow. In particular, fully silicided metal gates may be manufactured in conjunction with the e-fuse, without jeopardizing the correct functioning of the e-fuse.

Abstract: When forming field effect transistors, a common problem is the formation of a Schottky barrier at the interface between a metal thin film in the gate electrode and a semiconductor material, typically polysilicon, formed thereupon. Fully silicided gates are known in the state of the art which may overcome this problem. The claimed method proposes an improved fully silicided gate achieved by forming a gate structure including an additional metal layer between the metal gate layer and the gate semiconductor material. A silicidation process can then be optimized so as to form a lower metal silicide layer comprising the metal of the additional metal layer and an upper metal silicide layer forming an interface with the lower metal silicide layer.

Abstract: An illustrative semiconductor device disclosed herein includes a semiconductor substrate. The semiconductor substrate includes a first semiconductor material. In the first semiconductor material, a recess is provided. The recess is filled with a second semiconductor material having a different composition than the first semiconductor material. The semiconductor device further includes a first transistor including a source region, a drain region, a gate electrode and a channel region below the gate electrode. The channel region is arranged at two or more laterally opposite sides of the drain region. The source region is arranged at two or more laterally opposite sides of the channel region. The drain region includes a low doped drift region and a highly doped region. A dopant concentration in the low doped drift region is at least one of smaller than a dopant concentration in the highly doped region and approximately zero. At least the low doped drift region is provided in the second semiconductor material.

Abstract: Semiconductor device structures and methods for forming a semiconductor device are provided. In embodiments, one or more fins are provided, each of the one or more fins having a lower portion and an upper portion disposed on the lower portion. The lower portion is embedded in a first insulating material. The shape of the upper portion is at least one of a substantially triangular shape and a substantially rounded shape and a substantially trapezoidal shape. Furthermore, a layer of a second insulating material different from the first insulating material is formed on the upper portion.

Abstract: Methods are provided for fabricating an integrated circuit that includes gate to active contacts. One method includes forming a dummy gate structure including a dummy gate electrode having sidewalls and overlying a semiconductor substrate and first and second sidewall spacers on the sidewalls of the dummy gate electrode. The method includes removing the dummy gate electrode to form a trench bounded by the first and second sidewall spacers. The method removes an upper portion of the first sidewall spacer and deposits a layer of metal in the trench and over a remaining portion of the first sidewall spacer to form a gate electrode and an interconnect.

Abstract: A semiconductor device is provided including a semiconductor substrate and a nanowire formed over the semiconductor substrate and wherein the nanowire includes a first layer exhibiting tensile stress and a second layer exhibiting compressive stress.

Abstract: A semiconductor structure comprises a substrate and a transistor. The transistor comprises a raised source region and a raised drain region provided above the substrate, one or more elongated semiconductor lines, a gate electrode and a gate insulation layer. The one or more elongated semiconductor lines are connected between the raised source region and the raised drain region, wherein a longitudinal direction of each of the one or more elongated semiconductor lines extends substantially along a horizontal direction that is perpendicular to a thickness direction of the substrate. Each of the elongated semiconductor lines comprises a channel region. The gate electrode extends all around each of the channel regions of the one or more elongated semiconductor lines. The gate insulation layer is provided between each of the one or more elongated semiconductor lines and the gate electrode.

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided herein. In an embodiment, a method for fabricating an integrated circuit includes forming over a semiconductor substrate a gate structure. The method further includes depositing a non-conformal spacer material around the gate structure. A protection mask is formed over the non-conformal spacer material. The method etches the non-conformal spacer material and protection mask to form a salicidation spacer. Further, a self-aligned silicide contact is formed adjacent the salicidation spacer.

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing an ultrathin body (UTB) fully depleted silicon-on-insulator (FDSOI) substrate. A PFET temporary gate structure and an NFET temporary gate structure are formed on the substrate. The method implants ions to form lightly doped active areas around the gate structures. A diffusionless annealing process is performed on the active areas. Further, a compressive strain region is formed around the PFET gate structure and a tensile strain region is formed around the NFET gate structure.

Abstract: A structure comprises a semiconductor substrate, a semiconductor-on-insulator region and a bulk region. The semiconductor-on-insulator region comprises a first semiconductor region, a dielectric layer provided between the semiconductor substrate and the first semiconductor region, and a first transistor comprising an active region provided in the first semiconductor region. The dielectric layer provides electrical isolation between the first semiconductor region and the semiconductor substrate. The bulk region comprises a second semiconductor region provided directly on the semiconductor substrate.

Abstract: When forming sophisticated P-channel transistors, a semiconductor alloy layer is formed on the surface of the semiconductor layer including the transistor active region. When a metal silicide layer is formed contiguous to this semiconductor alloy layer, an agglomeration of the metal silicide layer into isolated clusters is observed. In order to solve this problem, the present invention proposes a method and a semiconductor device wherein the portion of the semiconductor alloy layer lying on the source and drain regions of the transistor is removed before formation of the metal silicide layer is performed. In this manner, the metal silicide layer is formed so as to be contiguous to the semiconductor layer, and not to the semiconductor alloy layer.

Abstract: Generally, the present disclosure is directed to methods for forming dual embedded stressor regions in semiconductor devices such as transistor elements and the like, using in situ doping and substantially diffusionless annealing techniques. One illustrative method disclosed herein includes forming first and second cavities in PMOS and NMOS device regions, respectively, of a semiconductor substrate, and thereafter performing first and second epitaxial deposition processes to form in situ doped first and second embedded material regions in the first and second cavities, respectively. The method further includes, among other things, performing a single heat treating process to activate dopants in the in situ doped first and second embedded material regions.

Abstract: The present invention relates to a semiconductor structure comprising at least a first and a second three-dimensional transistor, wherein the first transistor and the second transistor are electrically connected in parallel to each other, and wherein each transistor comprises a source and a drain, wherein the source and/or drain of the first transistor is at least partially separated from, respectively, the source and/or drain of the second transistor. The invention further relates to a process for realizing such a semiconductor structure.

Abstract: A semiconductor structure comprises a substrate and a transistor. The transistor comprises a raised source region and a raised drain region provided above the substrate, one or more elongated semiconductor lines, a gate electrode and a gate insulation layer. The one or more elongated semiconductor lines are connected between the raised source region and the raised drain region, wherein a longitudinal direction of each of the one or more elongated semiconductor lines extends substantially along a horizontal direction that is perpendicular to a thickness direction of the substrate. Each of the elongated semiconductor lines comprises a channel region. The gate electrode extends all around each of the channel regions of the one or more elongated semiconductor lines. The gate insulation layer is provided between each of the one or more elongated semiconductor lines and the gate electrode.