Patents by Inventor Stefan Jakschik
Stefan Jakschik has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8445963Abstract: A multi-gate device is disclosed. In one aspect, the device includes a substrate having a first semiconductor layer of a first carrier mobility enhancing parameter, a buried insulating layer, and a second semiconductor layer with a second carrier mobility enhancing parameter. The device also includes a first active region electrically isolated from a second active region in the substrate. The first active region has a first fin grown on the first semiconductor layer and having the first mobility enhancing parameter. The second active region has a second fin grown on the second semiconductor layer and having the second mobility enhancing parameter. The device also includes a dielectric layer over the second semiconductor layer which is located between the first fin and the second fin. The first and second fins protrude through and above the dielectric layer.Type: GrantFiled: November 19, 2010Date of Patent: May 21, 2013Assignee: IMECInventors: Stefan Jakschik, Nadine Collaert
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Patent number: 8344438Abstract: The present invention refers to an electrode comprising a first metallic layer and a compound comprising at least one of a nitride, oxide, and oxynitride of a second metallic material.Type: GrantFiled: January 31, 2008Date of Patent: January 1, 2013Assignee: Qimonda AGInventors: Uwe Schroeder, Stefan Jakschik, Johannes Heitmann, Tim Boescke, Annette Saenger
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Patent number: 8138538Abstract: One embodiment relates to an integrated circuit formed on a semiconductor body having interconnect between source/drain regions of a first and second transistor. The interconnect includes a metal body arranged underneath the surface of the semiconductor body. A contact element establishes electrical contact between the metal body and the source/drain regions of the first and second transistor. The contact element extends along a connecting path between the source/drain regions of the first and second transistors. Other methods, devices, and systems are also disclosed.Type: GrantFiled: October 10, 2008Date of Patent: March 20, 2012Assignee: Qimonda AGInventors: Hans-Peter Moll, Gouri Sankar Kar, Martin Popp, Lars Heineck, Peter Lahnor, Arnd Scholz, Stefan Jakschik, Wolfgang Roesner, Gerhard Enders, Werner Graf, Peter Baars, Klaus Muemmler, Bernd Hintze, Andrei Josiek
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Publication number: 20110068375Abstract: A multi-gate device is disclosed. In one aspect, the device includes a substrate having a first semiconductor layer of a first carrier mobility enhancing parameter, a buried insulating layer, and a second semiconductor layer with a second carrier mobility enhancing parameter. The device also includes a first active region electrically isolated from a second active region in the substrate. The first active region has a first fin grown on the first semiconductor layer and having the first mobility enhancing parameter. The second active region has a second fin grown on the second semiconductor layer and having the second mobility enhancing parameter. The device also includes a dielectric layer over the second semiconductor layer which is located between the first fin and the second fin. The first and second fins protrude through and above the dielectric layer.Type: ApplicationFiled: November 19, 2010Publication date: March 24, 2011Applicant: IMECInventors: Stefan Jakschik, Nadine Collaert
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Patent number: 7851297Abstract: A dual workfunction semiconductor device which comprises a first and second control electrode comprising a metal-semiconductor compound, e.g. a silicide or a germanide, and a dual workfunction semiconductor device thus obtained are disclosed. In one aspect, the method comprises forming a blocking region for preventing diffusion of metal from the metal-semiconductor compound of the first control electrode to the metal-semiconductor compound of the second control electrode, the blocking region being formed at a location where an interface between the first and second control electrodes is to be formed or is formed. By preventing metal to diffuse from the one to the other control electrode the constitution of the metal-semiconductor compounds of the first and second control electrodes may remain substantially unchanged during e.g. thermal steps in further processing of the device.Type: GrantFiled: June 24, 2008Date of Patent: December 14, 2010Assignee: IMECInventors: Stefan Jakschik, Jorge Adrian Kittl, Marcus Johannes Henricus van Dal, Anne Lauwers, Masaaki Niwa
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Patent number: 7842977Abstract: A gate electrode structure comprises at least one bi-layer, wherein each bi-layer comprises a plating film and a stress amplifier film. The plating film includes a poly-crystalline material. The stress amplifier film determines the crystallization result of the poly-crystalline material, wherein a mechanical stress induced through the plating layer is amplified. Tensile or compressive strain may be induced in a crystalline substrate. Electron or hole mobility may be increased and on-resistance characteristics of a MOS field effect transistor may be improved.Type: GrantFiled: February 15, 2007Date of Patent: November 30, 2010Assignee: Qimonda AGInventors: Stefan Jakschik, Thomas Hecht
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Patent number: 7842559Abstract: A method of fabricating a multi-gate device is disclosed. In one aspect, the method includes providing a substrate having a first semiconductor layer with a first carrier mobility enhancing parameter, an insulating layer, a second semiconductor layer with a second carrier mobility enhancing parameter different from the first carrier mobility enhancing parameter. A first and second dielectric layer are then provided on the substrate. A first trench is formed in a first active region through the dielectric layers, the second semiconductor layer and the buried insulating layer. A first fin is formed in the first trench, protruding above the first dielectric layer and having the first carrier mobility enhancing parameter. A second trench is formed in a second active region through the dielectric layers. A second fin is formed in the second trench, protruding above the first dielectric layer and having the second mobility enhancing parameter.Type: GrantFiled: December 19, 2008Date of Patent: November 30, 2010Assignee: IMECInventors: Stefan Jakschik, Nadine Collaert
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Publication number: 20100110753Abstract: An integrated circuit includes a plurality of switching devices, wherein each device includes a gate dielectric capable of assuming at least a first and a second polarization state. The integrated circuit further includes an address circuit configured to control bit lines electrically coupled to first load regions of a load path of the switching devices and a word line electrically coupled to gate electrodes of the switching devices. The address circuit is configured to control a write cycle such that a first voltage is induced at the gate dielectrics of selected ones of the switching devices and a second voltage is induced at the gate dielectrics of non-selected ones of the switching devices. The first voltage suffices to switch the gate dielectrics of the selected devices from the first to the second polarization state and the second voltage does not suffice to switch the gate dielectrics of the non-selected devices.Type: ApplicationFiled: October 31, 2008Publication date: May 6, 2010Applicant: QIMONDA AGInventors: Stefan Slesazeck, Rolf Weis, Stefan Jakschik
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Publication number: 20100090264Abstract: One embodiment relates to an integrated circuit formed on a semiconductor body having interconnect between source/drain regions of a first and second transistor. The interconnect includes a metal body arranged underneath the surface of the semiconductor body. A contact element establishes electrical contact between the metal body and the source/drain regions of the first and second transistor. The contact element extends along a connecting path between the source/drain regions of the first and second transistors. Other methods, devices, and systems are also disclosed.Type: ApplicationFiled: October 10, 2008Publication date: April 15, 2010Applicant: Qimonda AGInventors: Hans-Peter Moll, Gouri Sankar Kar, Martin Popp, Lars Heineck, Peter Lahnor, Arnd Scholz, Stefan Jakschik, Wolfgang Roesner, Gerhard Enders, Werner Graf, Peter Baars, Klaus Muemmler, Bernd Hintze, Andrei Josiek
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Publication number: 20090194410Abstract: The present invention refers to an electrode comprising a first metallic layer and a compound comprising at least one of a nitride, oxide, and oxynitride of a second metallic material.Type: ApplicationFiled: January 31, 2008Publication date: August 6, 2009Inventors: Uwe Schroeder, Stefan Jakschik, Johannes Heitmann, Tim Boescke, Annette Saender
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Publication number: 20090159972Abstract: A method of fabricating a multi-gate device is disclosed. In one aspect, the method includes providing a substrate having a first semiconductor layer with a first carrier mobility enhancing parameter, an insulating layer, a second semiconductor layer with a second carrier mobility enhancing parameter different from the first carrier mobility enhancing parameter. A first and second dielectric layer are then provided on the substrate. A first trench is formed in a first active region through the dielectric layers, the second semiconductor layer and the buried insulating layer. A first fin is formed in the first trench, protruding above the first dielectric layer and having the first carrier mobility enhancing parameter. A second trench is formed in a second active region through the dielectric layers. A second fin is formed in the second trench, protruding above the first dielectric layer and having the second mobility enhancing parameter.Type: ApplicationFiled: December 19, 2008Publication date: June 25, 2009Applicant: INTERUNIVERSITAIR MICROELEKTRONICA CENTRUM VZW (IMEC)Inventors: Stefan Jakschik, Nadine Collaert
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Patent number: 7531406Abstract: An electrical component, such as a DRAM semiconductor memory or a field-effect transistor is fabricated. At least one capacitor having a dielectric (130) and at least one connection electrode (120, 140) are fabricated. To enable the capacitors fabricated to have optimum storage properties even for very small capacitor structures, the dielectric (130) or the connection electrode (120, 140) are formed in such a manner that transient polarization effects are prevented or at least reduced.Type: GrantFiled: April 7, 2006Date of Patent: May 12, 2009Assignee: Infineon Technologies AGInventors: Alejandro Avellan, Thomas Hecht, Stefan Jakschik, Uwe Schroeder
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Publication number: 20090020821Abstract: A dual workfunction semiconductor device which comprises a first and second control electrode comprising a metal-semiconductor compound, e.g. a silicide or a germanide, and a dual workfunction semiconductor device thus obtained are disclosed. In one aspect, the method comprises forming a blocking region for preventing diffusion of metal from the metal-semiconductor compound of the first control electrode to the metal-semiconductor compound of the second control electrode, the blocking region being formed at a location where an interface between the first and second control electrodes is to be formed or is formed. By preventing metal to diffuse from the one to the other control electrode the constitution of the metal-semiconductor compounds of the first and second control electrodes may remain substantially unchanged during e.g. thermal steps in further processing of the device.Type: ApplicationFiled: June 24, 2008Publication date: January 22, 2009Applicant: Interuniversitair Microelektronica Centrum vzw (IMEC)Inventors: Stefan Jakschik, Jorge Adrian Kittl, Marcus Johannes Henricus van Dal, Anne Lauwers, Masaaki Niwa
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Publication number: 20080296680Abstract: A method of making an integrated circuit including doping a fin is disclosed. The method includes providing a substrate having at least one fin of a semiconductor material and carrying out a gas-phase doping of the at least one fin.Type: ApplicationFiled: May 30, 2007Publication date: December 4, 2008Applicant: QIMONDA AGInventors: Matthias Goldbach, Stefan Jakschik
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Publication number: 20080242097Abstract: The invention refers to a selective deposition method. A substrate comprising at least one structured surface is provided. The structured surface comprises a first area and a second area. The first area is selectively passivated regarding reactants of a first deposition technique and the second area is activated regarding the reactants the first deposition technique. A passivation layer on the second area is deposited via the first deposition technique. The passivation layer is inert regarding a precursors selected from a group of oxidizing reactants. A layer is deposited in the second area using a second atomic layer deposition technique as second deposition technique using the precursors selected form the group of oxidizing reactants.Type: ApplicationFiled: March 28, 2007Publication date: October 2, 2008Inventors: Tim Boescke, Annette Saenger, Stefan Jakschik, Christian Fachmann, Matthias Patz, Alejandro Avellan, Thomas Hecht, Jonas Sundqvist
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Publication number: 20080197428Abstract: A gate electrode structure comprises at least one bi-layer, wherein each bi-layer comprises a plating film and a stress amplifier film. The plating film includes a poly-crystalline material. The stress amplifier film determines the crystallization result of the poly-crystalline material, wherein a mechanical stress induced through the plating layer is amplified. Tensile or compressive strain may be induced in a crystalline substrate. Electron or hole mobility may be increased and on-resistance characteristics of a MOS field effect transistor may be improved.Type: ApplicationFiled: February 15, 2007Publication date: August 21, 2008Applicant: Qimonda AGInventors: Stefan Jakschik, Thomas Hecht
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Patent number: 7413951Abstract: A method produces stacked capacitors for dynamic memory cells, in which a number of trenches (48) are formed in the masking layer (40), each trench (48) being arranged above a respective contact plug (26) and extending from the top (42) of the masking layer (40) to the contact plugs (26). A conductive layer (50) covers the side walls (49) of the trenches (48) and the contact plugs (26) in order to form a first electrode (60) of a stacked capacitor (12). In an upper region (63), which is remote from the contact stack (26), the conductive layer (50) is replaced by an insulating layer, so that it is not possible for a short circuit to arise in the event of any adhesion between adjacent electrodes.Type: GrantFiled: September 7, 2006Date of Patent: August 19, 2008Assignee: Qimonda AGInventors: Stephan Kudelka, Peter Moll, Stefan Jakschik, Odo Wunnicke
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Patent number: 7358187Abstract: The present invention provides a coating process for patterned substrate surfaces, in which a substrate (101) is provided, the substrate having a surface (105) which is patterned in a substrate patterning region (102) and has one or more trenches (106) that are to be filled to a predetermined filling height (205), a catalyst layer (201) is introduced into the trenches (106) that are to be filled, a reaction layer (202) is deposited catalytically in the trenches (106) that are to be filled, the catalytically deposited reaction layer (202) is densified in the trenches (106) that are to be filled, and the introduction of the catalyst layer (201) and the catalytic deposition of the reaction layer (202) are repeated until the trenches (106) that are to be filled have been filled to the predetermined filling height (205).Type: GrantFiled: June 8, 2005Date of Patent: April 15, 2008Assignee: Infineon Technologies AGInventors: Thomas Hecht, Stefan Jakschik, Uwe Schröder
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Patent number: 7307735Abstract: The present invention relates to a method for determining the depth of a buried structure in a semiconductor wafer. According to the invention, the layer behavior of the semiconductor wafer which is brought about by the buried structure when the semiconductor wafer is irradiated with electromagnetic radiation in the infrared range and arises as a result of the significantly longer wavelengths of the radiation used in comparison with the lateral dimensions of the buried structure is utilized to determine the depth of the buried structure by spectrometric and/or ellipsometric methods.Type: GrantFiled: April 30, 2004Date of Patent: December 11, 2007Assignee: Infineon Technologies AGInventors: Thomas Hecht, Uwe Schröder, Ulrich Mantz, Stefan Jakschik, Andreas Orth
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Patent number: 7268037Abstract: A process for modifying sections of a semiconductor includes covering the sections to remain free of doping with a metal oxide, e.g., aluminum oxide. Then, the semiconductor is doped, for example, from the gas phase, in those sections that are not covered by the aluminum oxide. Finally, the aluminum oxide is selectively removed again, for example using hot phosphoric acid. Sections of the semiconductor surface which are formed from silicon, silicon oxide or silicon nitride remain in place on the wafer.Type: GrantFiled: January 24, 2005Date of Patent: September 11, 2007Assignee: Infineon Technologies, AGInventors: Stefan Jakschik, Thomas Hecht, Uwe Schröder, Matthias Goldbach