Abstract: The invention relates to a circuit arrangement and a method for operating an electric motor in a direct voltage source, in particular for operating a permanent-magnet-excited DC motor in the direct voltage network of a motor vehicle, having a rotary position transducer (32) for detecting the rotary position of the rotor (20), and having an electronic commutation controller (32) for switching over the current in the armature winding of the stator (12) as a function of the position of the rotor (20). It is proposed that the rotary position transducer (32) is positioned relative to the stator (12) for an early commutation, and that the actual commutation time can be set by means of a delay correction, ascertained by measurement separately for each motor (10), in the electronic commutation controller (30).

Abstract: A system for protecting a power semiconductor output stage that, as a function of a control signal, connects an inductive load to a direct-current supply voltage and disconnects it therefrom. Protection from the induced voltages is achieved, without a freewheeling diode, in that the disconnection energy occurring at the inductive load upon disconnection can be transferred in transformer fashion to an additional inductance that is loaded with a resistance or is coupled in the countercurrent direction to the direct-current supply voltage.

Abstract: A bondwire transition arrangement for interconnecting a signal port on one IC of a multichip module with a signal port on another, adjacent, IC of the same module employs a distributed signal-transition process in which the signal on one port appears as subsignals at tapping points along a series transmission-line segment arrangement between that port and ground on the same IC and the subsignals are recombined along a second series transmission-line segment arrangement connected between the other port and ground on the other IC. Spatially corresponding tapping points are interconnected via bondwires.

Abstract: System (50), e.g. a System on a chip (SoC), comprising a system bus (56), a high-speed functional block (51) operably linked to the system bus (56), and a high-speed clock line (54) for applying a high-speed clock to the high-speed functional block (51). The system (50) further comprises a peripheral bus (59), a low-speed functional block (52) operably linked to this peripheral bus (59), a circuitry (53) for generating a wait signal (PWAIT), a low-speed clock line (57) for applying a low-speed clock (PCLK) to the low-speed functional block (52), a select line (58) for feeding a select signal (PSEL) from the peripheral bus (59) to the low-speed functional block (52), an enable line (55) for applying a clock enable signal (PCLKEN) to the circuitry (53), and a wait line (61) for feeding the wait signal (PWAIT) to the high-speed functional block (51). The circuitry (53) generates the wait signal (PWAIT) from the select line signal (PSEL) and the clock enable signal (PCLKEN).

Abstract: A multicell amplifier comprises a first divider unit, which receives the input signal of the amplifier, divides it into 2N subsignals, amplifies them and recombines the amplified signals in two N-way combiners to form two local output signals; two further divider units which take the local output signals and divide them into 4N subsignals, amplify them and recombine the amplified signals to form three local output signals; and two combiner units which take the three local output signals and divide them into 4N subsignals, amplify them and recombine the amplified signals to provide the output signal of the amplifier.

Abstract: The invention relates to an integrated semiconductor mixer, having a substrate (10), a radio-frequency balun (12) disposed on the substrate (10), a local oscillator balun (14) disposed on the substrate (10), an intermediate-frequency port (16) disposed on the substrate (10), and a mixer diode array (18), disposed on the substrate (10), that communicates with the radio-frequency balun (12), the local oscillator balun (14), and the intermediate-frequency port (16), in which the radio-frequency balun (12) is shielded from the local oscillator balun (14) by plated holes (20).

Abstract: This invention relates to the structure and design of microprocessor ICs, in particular to the embedding or integration of a non-volatile, so-called flash memory into an ICs. Such a flash memory may be integrated by providing a dedicated flash bus which operationally links the flash memory with one or more microprocessors on the IC. Unfortunately, flash memories have relatively long access times compared to usual modern microprocessors. To achieve that the flash memory keeps pace with the microprocessor(s), a dedicated flash bus (2) links the flash memory (1) to the microprocessor (3), said flash bus (2) having a width m which is greater than the width n of the microprocessor's data bus (8). Preferably, width m is a multiple of width n. A plurality of intermediate storage registers (4) connects the flash bus (2) with the data bus (8) of the microprocessor (3) for performing the width conversion.

Abstract: An electronically commutatable motor, in particular for a fluid pump, includes excitation windings that may be connected to and disconnected from a DC supply voltage via semiconductor switches that are controlled by control signals of a commutation device. Additional closed- and/or open-loop control of the output of the motor, is obtained with a temperature protection system in that the control signals of the commutation device are clocked by pulse width modulatable output signals of a PWM generator and in that the pulse width ratio of the output signals of the PWM generator may additionally be modified as a function of the output signal of the temperature sensor.

Abstract: Antibody binding to the SEMP1 antigen and characterized in that said antibody binds to SEMP1 in a manner equivalent to an antibody selected from the group of antibodies DSM ACC2458, DSM ACC2459, DSM ACC2461, and DSM ACC2463 is useful for cancer diagnosis and therapy.

Abstract: This invention relates to the structure and design of microprocessor ICs, in particular to the embedding or integration of a non-volatile flash memory (7) into an IC. To integrate such a flash memory into an IC raises some problems which are solved by providing a dedicated flash bus (3) which operationally links the flash memory (7) with one or more microprocessors (1, 2) on the IC. Preferably, the flash bus (3) controls the flash-memory-specific commands and has a width greater than, in particular a multiple of, the width of the microprocessor (1, 2) and/or the flash memory (7) to compensate for the relatively slow access time of the flash memory. It is especially advantageous to structure the system as a master/slave bus system for operating the flash memory (7) and to link the flash bus via bridges (4, 5, 6) to the microprocessor/s (1, 2,) and through a shell (8) to the flash memory (7). For operating such a system, a flash bus arbiter (9) may be necessary or advantageous.

Abstract: An electronic circuit which has a voltage terminal, a switch, a voltage stabilizer and a computer. In addition, an interface terminal is provided, via which the computer can exchange data via an interface. After a supply voltage is applied at the voltage terminal, the switch (11) is initially closed so that the circuit has an extremely low quiescent current. A signal at the interface terminal causes the switch to close and the voltage stabilizer and the computer are activated.

Abstract: System (50), e.g. a System on a chip (SoC), comprising a system bus (56), a high-speed functional block (51) operably linked to the system bus (56), and a high-speed clock line (54) for applying a high-speed clock to the high-speed functional block (51). The system (50) further comprises a peripheral bus (59), a low-speed functional block (52) operably linked to this peripheral bus (59), a circuitry (53) for generating a wait signal (PWAIT), a low-speed clock line (57) for applying a low-speed clock (PCLK) to the low-speed functional block (52), a select line (58) for feeding a select signal (PSEL) from the peripheral bus (59) to the low-speed functional block (52), an enable line (55) for applying a clock enable signal (PCLKEN) to the circuitry (53), and a wait line (61) for feeding the wait signal (PWAIT) to the high-speed functional block (51). The circuitry (53) generates the wait signal (PWAIT) from the select line signal (PSEL) and the clock enable signal (PCLKEN).

Abstract: Antibody binding to the SEMP1 antigen and characterized in that said antibody binds to SEMP1 in a manner equivalent to an antibody selected from the group of antibodies DSM ACC2458, DSM ACC2459, DSM ACC2461, and DSM ACC2463 is useful for cancer diagnosis and therapy.

Abstract: An electronically commutated electric motor, has a rotor energized by permanent magnets; a stator provided with windings; a control electronic unit which supplies the windings of the stator with current in a low frequency cycle depending on a detected position of the rotor; commutator detecting means which detect the position of the rotor, the control electronic unit attenuating individual current supply periods of the windings to be supplied with current per unit time.

Abstract: In a pump, particularly for cooling water, with an impeller wheel (2) that is supported so that it can rotate in a pump chamber (6), an excitation device (12) for driving the impeller wheel (12) to rotate, and a control circuit (19) for the excitation device (12), the control circuit (19) and the excitation device (12) are thermally separated from one another by the pump chamber (6). The waste heat of the excitation device (12) is removed by the fluid circulating in the pump chamber (6) to the extent that the control circuit (19) is prevented from overheating.

Abstract: An electronic ballast for at least one low-pressure discharge lamp contains an inverter which is connected to a direct-voltage source (UBUS), a load circuit which is connected to the inverter and contains the lamp (LA) and a series resonant circuit, and an evaluating circuit arrangement (M1) which reacts to different operating states of the lamp (LA) and in the case of a defect or removal of the lamp (LA) generates corresponding signals for switching off the inverter. A heating transformer, for heating the coils (W1, W2), the primary winding (Tp) of which is connected in series with a switch (S3) to the output of the inverter and in any case is connected to the direct-voltage source (UBUS) if the inverter is switched off on account of the heating-coil defect or the removal of the lamp (LA), with the switch (S3) being clocked in this off-phase.

Abstract: A circuit for heating a component is maintained at a predefined operating temperature by a resistance heating element. A control system for the temperature of the resistance heating element is provided. From a determination of the average electrical energy delivered to the resistance heating element, an analysis arrangement concludes that the predefined operating temperature of the component to be heated has been at least approximately reached.

Abstract: Process for the recognition of the rectifier effect appearing in a gas discharge lamp (G1, G2) and an electronic ballast, for the operation of gas discharge lamps (G1, G2), with which such a process finds employment. The electronic ballast includes a monitoring or control circuit (IC2) which monitors an operating parameter of a load circuit (E) of the electronic ballast, whereby this operating parameter corresponds to the lamp voltage or is dependent thereon. The monitoring circuit (IC2) integrates this monitored operating parameter over a full period and determines upon the presence of a rectifier effect if the integration result deviates from a predetermined integration desired value. Further, for the recognition of the rectifier effect, the duration of the positive and negative half-waves of the monitored parameter can be compared.

Abstract: A system (15) comprising at least two integrated processors (P1 and P2). These two processors (P1 and P2) are operably connected via a communication channel (17) for exchanging information. One processor (P1) has a processor bus (10), a shareable unit (13), and a DMA unit (11) with an external DMA channel (12). The DMA unit (11) and the sharable unit (13) are connected to the processor bus (10). The other processor (P2) has an access unit (21) which is a connectable to the external DMA channel (12) of the DMA unit (11). Due to this arrangement, a communication channel (17) can be established from the access unit (21) which is connectable to the external DMA channel (12), the DMA unit (11), and the processor bus (10).

Abstract: The invention relates to an electronic apparatus (1) whose housing (2) is provided with a housing part that is constructed as a lever element (3) and whose hardness exceeds the hardness of crown caps so as to avoid damaging of the edges of a mobile telephone (1). To this end, the battery compartment of the mobile telephone is covered by means of an angled metal plate.