Patents by Inventor Stefan KRIVEC

Stefan KRIVEC has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220093483
    Abstract: A semiconductor device includes a contact metallization layer that includes aluminum and is arranged on a semiconductor substrate, an inorganic passivation structure arranged on the semiconductor substrate, an organic passivation layer comprising a first part that is arranged on the contact metallization layer, and a second part that is arranged on the inorganic passivation structure, a first layer structure including a first part that is in contact with the contact metallization layer, a second part that is contact with the inorganic passivation structure, and a third part that is disposed on the semiconductor substrate laterally between the inorganic passivation structure and the organic passivation layer.
    Type: Application
    Filed: November 30, 2021
    Publication date: March 24, 2022
    Inventors: Jens Peter Konrath, Wolfgang Bergner, Romain Esteve, Richard Gaisberger, Florian Grasse, Jochen Hilsenbeck, Ravi Keshav Joshi, Stefan Kramp, Stefan Krivec, Grzegorz Lupina, Hiroshi Narahashi, Andreas Voerckel, Stefan Woehlert
  • Patent number: 11217500
    Abstract: A semiconductor device includes a contact metallization layer arranged on a semiconductor substrate, an inorganic passivation structure arranged on the semiconductor substrate, and an organic passivation layer. The organic passivation layer is located between the contact metallization layer and the inorganic passivation structure, and located vertically closer to the semiconductor substrate than a part of the organic passivation layer located on top of the inorganic passivation structure.
    Type: Grant
    Filed: April 9, 2019
    Date of Patent: January 4, 2022
    Assignee: Infineon Technologies AG
    Inventors: Jens Peter Konrath, Wolfgang Bergner, Romain Esteve, Richard Gaisberger, Florian Grasse, Jochen Hilsenbeck, Ravi Keshav Joshi, Stefan Kramp, Stefan Krivec, Grzegorz Lupina, Hiroshi Narahashi, Andreas Voerckel, Stefan Woehlert
  • Patent number: 11195713
    Abstract: In one aspect, a method of forming a silicon-insulator layer is provided. The method includes arranging a silicon structure in a plasma etch process chamber and applying a plasma to the silicon structure in the plasma etch process chamber at a temperature of the silicon structure equal to or below 100° C. The plasma includes a component and a halogen derivate, thereby forming the silicon-insulator layer. The silicon-insulator layer includes silicon and the component. In another aspect, a semiconductor device is provided having a silicon-insulator layer formed by the method.
    Type: Grant
    Filed: May 30, 2019
    Date of Patent: December 7, 2021
    Assignee: Infineon Technologies AG
    Inventors: Joachim Hirschler, Georg Ehrentraut, Christoffer Erbert, Klaus Goeschl, Markus Heinrici, Michael Hutzler, Wolfgang Koell, Stefan Krivec, Ingmar Neumann, Mathias Plappert, Michael Roesner, Olaf Storbeck
  • Publication number: 20210265168
    Abstract: A process for producing an electrical contact with a first metal layer and at least one second metal layer on a silicon carbide substrate includes removing at least some of the carbon residue by a cleaning process, to clean the first metal layer. The first metal layer and/or the at least one second metal layer may be generated by sputtering deposition.
    Type: Application
    Filed: May 10, 2021
    Publication date: August 26, 2021
    Inventors: Stefan Krivec, Ronny Kern, Stefan Kramp, Gregor Langer, Hannes Winkler, Stefan Woehlert
  • Patent number: 11043383
    Abstract: A process for producing an electrical contact with a first metal layer and at least one second metal layer on a silicon carbide substrate includes removing at least some of the carbon residue by a chemical cleaning process, to clean the first metal layer. The first metal layer and/or the at least one second metal layer may be generated by sputtering deposition.
    Type: Grant
    Filed: May 24, 2019
    Date of Patent: June 22, 2021
    Assignee: Infineon Technologies AG
    Inventors: Stefan Krivec, Ronny Kern, Stefan Kramp, Gregor Langer, Hannes Winkler, Stefan Woehlert
  • Patent number: 10763339
    Abstract: A semiconductor device includes an n-doped monocrystalline semiconductor substrate having a substrate surface, an amorphous n-doped semiconductor surface layer at the substrate surface of the n-doped monocrystalline semiconductor substrate, and a Schottky-junction forming material in contact with the amorphous n-doped semiconductor surface layer. The Schottky-junction forming material forms at least one Schottky contact with the amorphous n-doped semiconductor surface layer.
    Type: Grant
    Filed: February 10, 2016
    Date of Patent: September 1, 2020
    Assignee: Infineon Technologies Austria AG
    Inventors: Jens Peter Konrath, Ronny Kern, Stefan Krivec, Ulrich Schmid, Laura Stoeber
  • Publication number: 20190385842
    Abstract: In one aspect, a method of forming a silicon-insulator layer is provided. The method includes arranging a silicon structure in a plasma etch process chamber and applying a plasma to the silicon structure in the plasma etch process chamber at a temperature of the silicon structure equal to or below 100° C. The plasma includes a component and a halogen derivate, thereby forming the silicon-insulator layer. The silicon-insulator layer includes silicon and the component. In another aspect, a semiconductor device is provided having a silicon-insulator layer formed by the method.
    Type: Application
    Filed: May 30, 2019
    Publication date: December 19, 2019
    Inventors: Joachim Hirschler, Georg Ehrentraut, Christoffer Erbert, Klaus Goeschl, Markus Heinrici, Michael Hutzler, Wolfgang Koell, Stefan Krivec, Ingmar Neumann, Mathias Plappert, Michael Roesner, Olaf Storbeck
  • Publication number: 20190362973
    Abstract: A process for producing an electrical contact with a first metal layer and at least one second metal layer on a silicon carbide substrate includes removing at least some of the carbon residue by a chemical cleaning process, to clean the first metal layer. The first metal layer and/or the at least one second metal layer may be generated by sputtering deposition.
    Type: Application
    Filed: May 24, 2019
    Publication date: November 28, 2019
    Inventors: Stefan Krivec, Ronny Kern, Stefan Kramp, Gregor Langer, Hannes Winkler, Stefan Woehlert
  • Publication number: 20190311966
    Abstract: A semiconductor device includes a contact metallization layer arranged on a semiconductor substrate, an inorganic passivation structure arranged on the semiconductor substrate, and an organic passivation layer. The organic passivation layer is located between the contact metallization layer and the inorganic passivation structure, and located vertically closer to the semiconductor substrate than a part of the organic passivation layer located on top of the inorganic passivation structure.
    Type: Application
    Filed: April 9, 2019
    Publication date: October 10, 2019
    Inventors: Jens Peter Konrath, Wolfgang Bergner, Romain Esteve, Richard Gaisberger, Florian Grasse, Jochen Hilsenbeck, Ravi Keshav Joshi, Stefan Kramp, Stefan Krivec, Grzegorz Lupina, Hiroshi Narahashi, Andreas Voerckel, Stefan Woehlert
  • Patent number: 10431698
    Abstract: According to an embodiment of a semiconductor device, the semiconductor device includes a contact layer in contact with SiC material. The contact layer includes a metal nitride having a nitrogen content in a range of 10 to 50 atomic %. The semiconductor device further includes a non-ohmic contact formed between the SiC material and the contact layer.
    Type: Grant
    Filed: January 2, 2019
    Date of Patent: October 1, 2019
    Assignee: Infineon Technologies Austria AG
    Inventors: Jens Peter Konrath, Ronny Kern, Stefan Krivec, Ulrich Schmid, Laura Stoeber
  • Patent number: 10393697
    Abstract: An apparatus for analyzing ion kinetics in a dielectric probe structure includes an ion reservoir abutting the dielectric probe structure and configured to supply mobile ions to the dielectric probe structure, a capacitor structure configured to generate an electric field in the dielectric probe structure along a vertical direction, and an electrode structure configured to generate an electrophoretic force on mobile ions in the dielectric probe structure along a lateral direction. A method for analyzing ion kinetics in the dielectric probe structure of the apparatus is also provided.
    Type: Grant
    Filed: November 2, 2015
    Date of Patent: August 27, 2019
    Assignee: Infineon Technologies AG
    Inventors: Sabine Gruber, Thomas Aichinger, Stefan Krivec, Thomas Ostermann
  • Patent number: 10361096
    Abstract: In various embodiments, a method is provided. The method includes forming a metallization layer above at least one first region of a substrate. After forming the metallization layer at least one second region of the substrate is free of the metallization layer. The method further includes forming a barrier layer above the at least one first region of the substrate and above the at least one second region of the substrate. The barrier layer in the at least one first region of the substrate directly adjoins the metallization layer. The method further includes removing the barrier layer in the at least one first region of the substrate by drive-in of the barrier layer into the metallization layer.
    Type: Grant
    Filed: August 15, 2017
    Date of Patent: July 23, 2019
    Assignee: Infineon Technologies AG
    Inventors: Mathias Plappert, Stefan Krivec, Andreas Riegler, Karin Schrettlinger
  • Publication number: 20190140111
    Abstract: According to an embodiment of a semiconductor device, the semiconductor device includes a contact layer in contact with SiC material. The contact layer includes a metal nitride having a nitrogen content in a range of 10 to 50 atomic %. The semiconductor device further includes a non-ohmic contact formed between the SiC material and the contact layer.
    Type: Application
    Filed: January 2, 2019
    Publication date: May 9, 2019
    Inventors: Jens Peter Konrath, Ronny Kern, Stefan Krivec, Ulrich Schmid, Laura Stoeber
  • Patent number: 10199514
    Abstract: An embodiment of a method of manufacturing a semiconductor device includes providing a semiconductor material that comprises SiC and forming an electrically conductive contact layer on the semiconductor material. A non-ohmic contact is formed between the semiconductor material and the electrically conductive contact layer. The electrically conductive contact layer comprises a metal nitride with a nitrogen content between 10 to 50 atomic %. Additional embodiments of manufacturing a semiconductor device are described.
    Type: Grant
    Filed: January 9, 2018
    Date of Patent: February 5, 2019
    Assignee: Infineon Technologies Austria AG
    Inventors: Jens Peter Konrath, Ronny Kern, Stefan Krivec, Ulrich Schmid, Laura Stoeber
  • Patent number: 9997459
    Abstract: A semiconductor device includes a semiconductor body having a front face, a back face and an active zone at the front face. A front surface metallization layer having a front face and a back face is disposed over the semiconductor body so that the back face of the front surface metallization layer faces the front face of the semiconductor body and is electrically connected to the active zone. An upper barrier layer made of amorphous molybdenum nitride is disposed on the front face of the front surface metallization layer.
    Type: Grant
    Filed: February 8, 2017
    Date of Patent: June 12, 2018
    Assignee: Infineon Technologies AG
    Inventors: Jochen Hilsenbeck, Jens Peter Konrath, Stefan Krivec
  • Publication number: 20180158964
    Abstract: An embodiment of a method of manufacturing a semiconductor device includes providing a semiconductor material that comprises SiC and forming an electrically conductive contact layer on the semiconductor material. A non-ohmic contact is formed between the semiconductor material and the electrically conductive contact layer. The electrically conductive contact layer comprises a metal nitride with a nitrogen content between 10 to 50 atomic %. Additional embodiments of manufacturing a semiconductor device are described.
    Type: Application
    Filed: January 9, 2018
    Publication date: June 7, 2018
    Inventors: Jens Peter Konrath, Ronny Kern, Stefan Krivec, Ulrich Schmid, Laura Stoeber
  • Patent number: 9929111
    Abstract: A method of manufacturing a layer structure includes: forming a first layer over a substrate; planarizing the first layer to form a planarized surface of the first layer; and forming a second layer over the planarized surface; wherein a porosity of the first layer is greater than a porosity of the substrate and greater than a porosity of the second layer; wherein the second layer is formed by physical vapor deposition; and wherein the first layer and the second layer are formed from the same solid material.
    Type: Grant
    Filed: March 17, 2017
    Date of Patent: March 27, 2018
    Assignee: Infineon Technologies AG
    Inventors: Martin Mischitz, Markus Heinrici, Barbara Eichinger, Manfred Schneegans, Stefan Krivec
  • Publication number: 20180053663
    Abstract: In various embodiments, a method is provided. The method includes forming a metallization layer above at least one first region of a substrate. After forming the metallization layer at least one second region of the substrate is free of the metallization layer. The method further includes forming a barrier layer above the at least one first region of the substrate and above the at least one second region of the substrate. The barrier layer in the at least one first region of the substrate directly adjoins the metallization layer. The method further includes removing the barrier layer in the at least one first region of the substrate by drive-in of the barrier layer into the metallization layer.
    Type: Application
    Filed: August 15, 2017
    Publication date: February 22, 2018
    Inventors: Mathias Plappert, Stefan Krivec, Andreas Riegler, Karin Schrettlinger
  • Publication number: 20170243828
    Abstract: A semiconductor device includes a semiconductor body with a front face and a back face, having an active zone located at the front face, a front surface metallization layer having a front face and a back face directed towards the active zone, the front surface metallization layer being provided on the front face of the semiconductor body and being electrically connected to the active zone, and a first barrier layer, including amorphous molybdenum nitride, located between the active zone and the metallization layer. Further, a method for producing such a device is provided.
    Type: Application
    Filed: February 8, 2017
    Publication date: August 24, 2017
    Inventors: Jochen Hilsenbeck, Jens Peter Konrath, Stefan Krivec
  • Publication number: 20170194272
    Abstract: A method of manufacturing a layer structure includes: forming a first layer over a substrate; planarizing the first layer to form a planarized surface of the first layer; and forming a second layer over the planarized surface; wherein a porosity of the first layer is greater than a porosity of the substrate and greater than a porosity of the second layer; wherein the second layer is formed by physical vapor deposition; and wherein the first layer and the second layer are formed from the same solid material.
    Type: Application
    Filed: March 17, 2017
    Publication date: July 6, 2017
    Inventors: Martin MISCHITZ, Markus HEINRICI, Barbara EICHINGER, Manfred SCHNEEGANS, Stefan KRIVEC