Patents by Inventor Stefan KRIVEC

Stefan KRIVEC has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9929111
    Abstract: A method of manufacturing a layer structure includes: forming a first layer over a substrate; planarizing the first layer to form a planarized surface of the first layer; and forming a second layer over the planarized surface; wherein a porosity of the first layer is greater than a porosity of the substrate and greater than a porosity of the second layer; wherein the second layer is formed by physical vapor deposition; and wherein the first layer and the second layer are formed from the same solid material.
    Type: Grant
    Filed: March 17, 2017
    Date of Patent: March 27, 2018
    Assignee: Infineon Technologies AG
    Inventors: Martin Mischitz, Markus Heinrici, Barbara Eichinger, Manfred Schneegans, Stefan Krivec
  • Publication number: 20180053663
    Abstract: In various embodiments, a method is provided. The method includes forming a metallization layer above at least one first region of a substrate. After forming the metallization layer at least one second region of the substrate is free of the metallization layer. The method further includes forming a barrier layer above the at least one first region of the substrate and above the at least one second region of the substrate. The barrier layer in the at least one first region of the substrate directly adjoins the metallization layer. The method further includes removing the barrier layer in the at least one first region of the substrate by drive-in of the barrier layer into the metallization layer.
    Type: Application
    Filed: August 15, 2017
    Publication date: February 22, 2018
    Inventors: Mathias Plappert, Stefan Krivec, Andreas Riegler, Karin Schrettlinger
  • Publication number: 20170243828
    Abstract: A semiconductor device includes a semiconductor body with a front face and a back face, having an active zone located at the front face, a front surface metallization layer having a front face and a back face directed towards the active zone, the front surface metallization layer being provided on the front face of the semiconductor body and being electrically connected to the active zone, and a first barrier layer, including amorphous molybdenum nitride, located between the active zone and the metallization layer. Further, a method for producing such a device is provided.
    Type: Application
    Filed: February 8, 2017
    Publication date: August 24, 2017
    Inventors: Jochen Hilsenbeck, Jens Peter Konrath, Stefan Krivec
  • Publication number: 20170194272
    Abstract: A method of manufacturing a layer structure includes: forming a first layer over a substrate; planarizing the first layer to form a planarized surface of the first layer; and forming a second layer over the planarized surface; wherein a porosity of the first layer is greater than a porosity of the substrate and greater than a porosity of the second layer; wherein the second layer is formed by physical vapor deposition; and wherein the first layer and the second layer are formed from the same solid material.
    Type: Application
    Filed: March 17, 2017
    Publication date: July 6, 2017
    Inventors: Martin MISCHITZ, Markus HEINRICI, Barbara EICHINGER, Manfred SCHNEEGANS, Stefan KRIVEC
  • Patent number: 9685347
    Abstract: A semiconductor device comprises a semiconductor body with a front face and a back face, having an active zone located at the front face, a front surface metallization layer having a front face and a back face directed towards the active zone, the front surface metallization layer being provided on the front face of the semiconductor body and being electrically connected to the active zone, and a first barrier layer, comprising amorphous metal nitride, located between the active zone and the metallization layer. Further, a method for producing such a device is provided.
    Type: Grant
    Filed: November 4, 2014
    Date of Patent: June 20, 2017
    Assignee: Infineon Technologies AG
    Inventors: Jochen Hilsenbeck, Jens Peter Konrath, Stefan Krivec
  • Publication number: 20170170282
    Abstract: In an embodiment, a method includes forming an adhesion promotion layer on at least portions of a conductive surface arranged on a Group III nitride-based semiconductor layer, applying a resist layer to the adhesion promotion layer such that regions of the conductive surface are uncovered by the adhesion promotion layer and the resist layer, applying by electroplating a conductive layer to the regions of the conductive surface uncovered by the adhesion promotion layer and the resist layer, and removing the resist layer and removing the adhesion promotion layer.
    Type: Application
    Filed: December 15, 2015
    Publication date: June 15, 2017
    Inventors: Arno Zechmann, Annette Saenger, Ulrike Fastner, Beate Weissnicht, Stefan Krivec
  • Patent number: 9660037
    Abstract: In an embodiment, a method includes forming an adhesion promotion layer on at least portions of a conductive surface arranged on a Group III nitride-based semiconductor layer, applying a resist layer to the adhesion promotion layer such that regions of the conductive surface are uncovered by the adhesion promotion layer and the resist layer, applying by electroplating a conductive layer to the regions of the conductive surface uncovered by the adhesion promotion layer and the resist layer, and removing the resist layer and removing the adhesion promotion layer.
    Type: Grant
    Filed: December 15, 2015
    Date of Patent: May 23, 2017
    Assignee: Infineon Technologies Austria AG
    Inventors: Arno Zechmann, Annette Sanger, Ulrike Fastner, Beate Weissnicht, Stefan Krivec
  • Patent number: 9620466
    Abstract: A method of manufacturing an electronic device may include: forming at least one electronic component in a substrate; forming a contact pad in electrical contact with the at least one electronic component; wherein forming the contact pad includes: forming a first layer over the substrate; planarizing the first layer to form a planarized surface of the first layer; and forming a second layer over the planarized surface, wherein the second layer has a lower porosity than the first layer.
    Type: Grant
    Filed: November 30, 2015
    Date of Patent: April 11, 2017
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Martin Mischitz, Markus Heinrici, Barbara Eichinger, Manfred Schneegans, Stefan Krivec
  • Patent number: 9599586
    Abstract: The disclosure describes techniques for determining an ion concentration in a sample. According to these techniques of this disclosure, an ion concentration of a sample is determined based on detecting at least one change in an electrical characteristic of a semiconductor device due to a gate insulation layer of the semiconductor device placed in contact with the sample.
    Type: Grant
    Filed: August 27, 2012
    Date of Patent: March 21, 2017
    Assignee: Infineon Technologies AG
    Inventors: Stefan Krivec, Guenter Schagerl
  • Patent number: 9595469
    Abstract: A semiconductor device includes a semiconductor body with a front face and a back face, having an active zone located at the front face, a front surface metallization layer having a front face and a back face directed towards the active zone, the front surface metallization layer being provided on the front face of the semiconductor body and being electrically connected to the active zone, and a first barrier layer, including amorphous molybdenum nitride, located between the active zone and the metallization layer. Further, a method for producing such a device is provided.
    Type: Grant
    Filed: November 4, 2013
    Date of Patent: March 14, 2017
    Assignee: Infineon Technologies AG
    Inventors: Jochen Hilsenbeck, Jens Peter Konrath, Stefan Krivec
  • Publication number: 20160276452
    Abstract: A semiconductor device includes an n-doped monocrystalline semiconductor substrate having a substrate surface, an amorphous n-doped semiconductor surface layer at the substrate surface of the n-doped monocrystalline semiconductor substrate, and a Schottky-junction forming material in contact with the amorphous n-doped semiconductor surface layer. The Schottky-junction forming material forms at least one Schottky contact with the amorphous n-doped semiconductor surface layer.
    Type: Application
    Filed: February 10, 2016
    Publication date: September 22, 2016
    Inventors: Jens Peter Konrath, Ronny Kern, Stefan Krivec, Ulrich Schmid, Laura Stoeber
  • Publication number: 20160211140
    Abstract: A method for processing a semiconductor includes irradiating a surface of a semiconductor with ions of a first gas type for cleaning the surface and implanting of ions of a second gas type in a region below the surface of the semiconductor for creating defects in the region below the surface. The irradiating and the implanting are performed within the same chamber.
    Type: Application
    Filed: January 15, 2016
    Publication date: July 21, 2016
    Inventors: Jens Peter Konrath, Ronny Kern, Stefan Krivec, Ulrich Schmid, Laura Stoeber
  • Publication number: 20160181441
    Abstract: A semiconductor device includes a semiconductor material having a bandgap larger than 2 eV and less than 10 eV, and a contact layer in contact with the semiconductor material. The contact layer includes a metal nitride. A non-ohmic contact is formed between the semiconductor material and the contact layer.
    Type: Application
    Filed: December 16, 2015
    Publication date: June 23, 2016
    Inventors: Jens Peter Konrath, Ronny Kern, Stefan Krivec, Ulrich Schmid, Laura Stoeber
  • Publication number: 20160139077
    Abstract: An apparatus for analyzing ion kinetics in a dielectric probe structure includes an ion reservoir abutting the dielectric probe structure and configured to supply mobile ions to the dielectric probe structure, a capacitor structure configured to generate an electric field in the dielectric probe structure along a vertical direction, and an electrode structure configured to generate an electrophoretic force on mobile ions in the dielectric probe structure along a lateral direction. A method for analyzing ion kinetics in the dielectric probe structure of the apparatus is also provided.
    Type: Application
    Filed: November 2, 2015
    Publication date: May 19, 2016
    Inventors: Sabine Gruber, Thomas Aichinger, Stefan Krivec, Thomas Ostermann
  • Publication number: 20160126197
    Abstract: A semiconductor device includes a semiconductor chip having a first main surface and a second main surface. A chip electrode is disposed on the first main surface. The chip electrode includes a first metal layer and wherein the first metal layer is arranged between the semiconductor chip and the second metal layer.
    Type: Application
    Filed: November 4, 2015
    Publication date: May 5, 2016
    Applicant: Infineon Technologies AG
    Inventors: Kurt Matoy, Dirk Ahlers, Ulrike Fastner, Petra Fischer, Karl-Heinz Gasser, Stephan Henneck, Stefan Krivec, Florian Weilnboeck
  • Publication number: 20150123145
    Abstract: A semiconductor device includes a semiconductor body with a front face and a back face, having an active zone located at the front face, a front surface metallization layer having a front face and a back face directed towards the active zone, the front surface metallization layer being provided on the front face of the semiconductor body and being electrically connected to the active zone, and a first barrier layer, including amorphous molybdenum nitride, located between the active zone and the metallization layer. Further, a method for producing such a device is provided.
    Type: Application
    Filed: November 4, 2013
    Publication date: May 7, 2015
    Inventors: Jochen Hilsenbeck, Jens Peter Konrath, Stefan Krivec
  • Publication number: 20150123149
    Abstract: A semiconductor device comprises a semiconductor body with a front face and a back face, having an active zone located at the front face, a front surface metallization layer having a front face and a back face directed towards the active zone, the front surface metallization layer being provided on the front face of the semiconductor body and being electrically connected to the active zone, and a first barrier layer, comprising amorphous metal nitride, located between the active zone and the metallization layer. Further, a method for producing such a device is provided.
    Type: Application
    Filed: November 4, 2014
    Publication date: May 7, 2015
    Inventors: Jochen Hilsenbeck, Jens Peter Konrath, Stefan Krivec
  • Publication number: 20140055145
    Abstract: The disclosure describes techniques for determining an ion concentration in a sample. According to these techniques of this disclosure, an ion concentration of a sample is determined based on detecting at least one change in an electrical characteristic of a semiconductor device due to a gate insulation layer of the semiconductor device placed in contact with the sample.
    Type: Application
    Filed: August 27, 2012
    Publication date: February 27, 2014
    Inventors: Stefan KRIVEC, Guenter SCHAGERL