Patents by Inventor Stefan Pompl
Stefan Pompl has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11916059Abstract: An ESD protection device may include: a first vertically integrated ESD protection structure comprising a first semiconductor portion, a first contact region disposed on a first side of the first semiconductor portion and a first terminal exposed on a second side of the first semiconductor portion opposite the first side of the first semiconductor portion, a second vertically integrated ESD protection structure comprising a second semiconductor portion, a second contact region disposed on a first side of the second semiconductor portion and a second terminal exposed on a second side of the second semiconductor portion opposite the first side of the second semiconductor portion, an electrical connection layer, wherein the first vertically integrated ESD protection structure and the second vertically integrated ESD protection structure are disposed on the electrical connection layer laterally separated from each other and are electrically connected with each other anti-serially via the electrical connection layType: GrantFiled: August 25, 2021Date of Patent: February 27, 2024Assignee: Infineon Technologies AGInventors: Andre Schmenn, Stefan Pompl, Damian Sojka, Katharina Umminger
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Publication number: 20220045046Abstract: An ESD protection device may include: a first vertically integrated ESD protection structure comprising a first semiconductor portion, a first contact region disposed on a first side of the first semiconductor portion and a first terminal exposed on a second side of the first semiconductor portion opposite the first side of the first semiconductor portion, a second vertically integrated ESD protection structure comprising a second semiconductor portion, a second contact region disposed on a first side of the second semiconductor portion and a second terminal exposed on a second side of the second semiconductor portion opposite the first side of the second semiconductor portion, an electrical connection layer, wherein the first vertically integrated ESD protection structure and the second vertically integrated ESD protection structure are disposed on the electrical connection layer laterally separated from each other and are electrically connected with each other anti-serially via the electrical connection layType: ApplicationFiled: August 25, 2021Publication date: February 10, 2022Inventors: Andre SCHMENN, Stefan POMPL, Damian SOJKA, Katharina UMMINGER
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Patent number: 11127733Abstract: An ESD protection device may include: a first vertically integrated ESD protection structure comprising a first semiconductor portion, a first contact region disposed on a first side of the first semiconductor portion and a first terminal exposed on a second side of the first semiconductor portion opposite the first side of the first semiconductor portion, a second vertically integrated ESD protection structure comprising a second semiconductor portion, a second contact region disposed on a first side of the second semiconductor portion and a second terminal exposed on a second side of the second semiconductor portion opposite the first side of the second semiconductor portion, an electrical connection layer, wherein the first vertically integrated ESD protection structure and the second vertically integrated ESD protection structure are disposed on the electrical connection layer laterally separated from each other and are electrically connected with each other anti-serially via the electrical connection layType: GrantFiled: February 6, 2020Date of Patent: September 21, 2021Assignee: Infineon Technologies AGInventors: Andre Schmenn, Stefan Pompl, Damian Sojka, Katharina Umminger
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Publication number: 20200176438Abstract: An ESD protection device may include: a first vertically integrated ESD protection structure comprising a first semiconductor portion, a first contact region disposed on a first side of the first semiconductor portion and a first terminal exposed on a second side of the first semiconductor portion opposite the first side of the first semiconductor portion, a second vertically integrated ESD protection structure comprising a second semiconductor portion, a second contact region disposed on a first side of the second semiconductor portion and a second terminal exposed on a second side of the second semiconductor portion opposite the first side of the second semiconductor portion, an electrical connection layer, wherein the first vertically integrated ESD protection structure and the second vertically integrated ESD protection structure are disposed on the electrical connection layer laterally separated from each other and are electrically connected with each other anti-serially via the electrical connection layType: ApplicationFiled: February 6, 2020Publication date: June 4, 2020Inventors: Andre SCHMENN, Stefan POMPL, Damian SOJKA, Katharina UMMINGER
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Patent number: 10672758Abstract: According an embodiment, an electrostatic discharge protection structure includes: a semiconductor layer doped with a dopant of a first doping type, a first well region extending from a surface of the semiconductor layer into the semiconductor layer, wherein the first well region is doped with a dopant of a second doping type opposite the first doping type; a second well region next to the first well region and extending from the surface of the semiconductor layer into the semiconductor layer, wherein the second well region is doped with a dopant of the first doping type; an isolation structure extending from the surface of the semiconductor layer into the semiconductor layer with a depth similar to the depth of at least one of the first well region or the second well region, wherein the isolation structure is arranged laterally adjacent to the first well region and the second well region.Type: GrantFiled: October 18, 2017Date of Patent: June 2, 2020Assignee: INFINEON TECHNOLOGIES AGInventors: Vadim Valentinovic Vendt, Stefan Pompl, Andre Schmenn, Joost Willemen
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Patent number: 10622346Abstract: A method for manufacturing an electronic device includes: providing a semiconductor carrier including first and second vertically integrated electronic structures laterally spaced apart from each other, an electrical connection layer disposed over a first side of the semiconductor carrier and electrically connecting the first and second vertically integrated electronic structures with each other; mounting the semiconductor carrier on a support carrier with the first side of the semiconductor carrier facing the support carrier; thinning the semiconductor carrier from a second side opposite the first side; and removing material of the semiconductor carrier in a separation region between the first and second vertically integrated electronic structures to separate a first semiconductor region of the first vertically integrated electronic structure from a second semiconductor region of the second vertically integrated electronic structure with the first and second vertically integrated electronic structures remainType: GrantFiled: September 29, 2017Date of Patent: April 14, 2020Assignee: INFINEON TECHNOLOGIES AGInventors: Andre Schmenn, Stefan Pompl, Damian Sojka, Katharina Umminger
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Publication number: 20180108648Abstract: According an embodiment, an electrostatic discharge protection structure includes: a semiconductor layer doped with a dopant of a first doping type, a first well region extending from a surface of the semiconductor layer into the semiconductor layer, wherein the first well region is doped with a dopant of a second doping type opposite the first doping type; a second well region next to the first well region and extending from the surface of the semiconductor layer into the semiconductor layer, wherein the second well region is doped with a dopant of the first doping type; an isolation structure extending from the surface of the semiconductor layer into the semiconductor layer with a depth similar to the depth of at least one of the first well region or the second well region, wherein the isolation structure is arranged laterally adjacent to the first well region and the second well region.Type: ApplicationFiled: October 18, 2017Publication date: April 19, 2018Inventors: Vadim Valentinovic Vendt, Stefan Pompl, Andre Schmenn, Joost Willemen
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Publication number: 20180096984Abstract: A method for manufacturing an electronic device includes: providing a semiconductor carrier including first and second vertically integrated electronic structures laterally spaced apart from each other, an electrical connection layer disposed over a first side of the semiconductor carrier and electrically connecting the first and second vertically integrated electronic structures with each other; mounting the semiconductor carrier on a support carrier with the first side of the semiconductor carrier facing the support carrier; thinning the semiconductor carrier from a second side opposite the first side; and removing material of the semiconductor carrier in a separation region between the first and second vertically integrated electronic structures to separate a first semiconductor region of the first vertically integrated electronic structure from a second semiconductor region of the second vertically integrated electronic structure with the first and second vertically integrated electronic structures remainType: ApplicationFiled: September 29, 2017Publication date: April 5, 2018Inventors: Andre SCHMENN, Stefan POMPL, Damian SOJKA, Katharina UMMINGER
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Patent number: 9881991Abstract: A method for manufacturing a semiconductor device and a semiconductor device are disclosed. The method comprises forming a trench in a substrate, partially filling the trench with a first semiconductive material, forming an interface along a surface of the first semiconductive material, and filling the trench with a second semiconductive material. The semiconductor device includes a first electrode arranged along sidewalls of a trench and a dielectric arranged over the first electrode. The semiconductor device further includes a second electrode at least partially filling the trench, wherein the second electrode comprises an interface within the second electrode.Type: GrantFiled: October 20, 2015Date of Patent: January 30, 2018Assignee: Infineon Technologies AGInventors: Wolfgang Lehnert, Michael Stadtmueller, Stefan Pompl, Markus Meyer
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Patent number: 9583559Abstract: In one embodiment a method of forming a compressive polycrystalline semiconductive material layer is disclosed. The method comprises forming a polycrystalline semiconductive seed layer over a substrate and forming a silicon layer by depositing silicon directly on the polycrystalline silicon seed layer under amorphous process conditions at a temperature below 600 C.Type: GrantFiled: March 23, 2015Date of Patent: February 28, 2017Assignee: Infineon Technologies AGInventors: Wolfgang Lehnert, Stefan Pompl, Markus Meyer
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Patent number: 9508790Abstract: A method of forming a semiconductor device includes forming an opening having a sidewall in a substrate and forming a first epitaxial layer in the opening. The first epitaxial layer is formed in a first portion of the sidewall without growing in a second portion of the sidewall. A second epitaxial layer is formed in the opening after forming the first epitaxial layer. The second epitaxial layer is formed in the second portion of the sidewall. The first epitaxial layer is removed after forming the second epitaxial layer.Type: GrantFiled: May 28, 2015Date of Patent: November 29, 2016Assignee: Infineon Technologies AGInventors: Thomas Popp, Stefan Pompl, Rudolf Berger
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Publication number: 20160043164Abstract: A method for manufacturing a semiconductor device and a semiconductor device are disclosed. The method comprises forming a trench in a substrate, partially filling the trench with a first semiconductive material, forming an interface along a surface of the first semiconductive material, and filling the trench with a second semiconductive material. The semiconductor device includes a first electrode arranged along sidewalls of a trench and a dielectric arranged over the first electrode. The semiconductor device further includes a second electrode at least partially filling the trench, wherein the second electrode comprises an interface within the second electrode.Type: ApplicationFiled: October 20, 2015Publication date: February 11, 2016Inventors: Wolfgang Lehnert, Michael Stadtmueller, Stefan Pompl, Markus Meyer
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Patent number: 9196675Abstract: A method for manufacturing a semiconductor device and a semiconductor device are disclosed. The method comprises forming a trench in a substrate, partially filling the trench with a first semiconductive material, forming an interface along a surface of the first semiconductive material, and filling the trench with a second semiconductive material. The semiconductor device includes a first electrode arranged along sidewalls of a trench and a dielectric arranged over the first electrode. The semiconductor device further includes a second electrode at least partially filling the trench, wherein the second electrode comprises an interface within the second electrode.Type: GrantFiled: January 31, 2014Date of Patent: November 24, 2015Assignee: Infineon Technologies AGInventors: Wolfgang Lehnert, Michael Stadtmueller, Stefan Pompl, Markus Meyer
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Publication number: 20150263083Abstract: A method of forming a semiconductor device includes forming an opening having a sidewall in a substrate and forming a first epitaxial layer in the opening. The first epitaxial layer is formed in a first portion of the sidewall without growing in a second portion of the sidewall. A second epitaxial layer is formed in the opening after forming the first epitaxial layer. The second epitaxial layer is formed in the second portion of the sidewall. The first epitaxial layer is removed after forming the second epitaxial layer.Type: ApplicationFiled: May 28, 2015Publication date: September 17, 2015Inventors: Thomas Popp, Stefan Pompl, Rudolf Berger
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Patent number: 9111781Abstract: A method of forming a semiconductor device includes forming an opening having a sidewall in a substrate and forming a first epitaxial layer in the opening. The first epitaxial layer is formed in a first portion of the sidewall without growing in a second portion of the sidewall. A second epitaxial layer is formed in the opening after forming the first epitaxial layer. The second epitaxial layer is formed in the second portion of the sidewall. The first epitaxial layer is removed after forming the second epitaxial layer.Type: GrantFiled: February 24, 2012Date of Patent: August 18, 2015Assignee: Infineon Technologies AGInventors: Thomas Popp, Stefan Pompl, Rudolf Berger
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Publication number: 20150194480Abstract: In one embodiment a method of forming a compressive polycrystalline semiconductive material layer is disclosed. The method comprises forming a polycrystalline semiconductive seed layer over a substrate and forming a silicon layer by depositing silicon directly on the polycrystalline silicon seed layer under amorphous process conditions at a temperature below 600 C.Type: ApplicationFiled: March 23, 2015Publication date: July 9, 2015Inventors: Wolfgang Lehnert, Stefan Pompl, Markus Meyer
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Patent number: 9012295Abstract: In one embodiment a method of forming a compressive polycrystalline semiconductive material layer is disclosed. The method comprises forming a polycrystalline semiconductive seed layer over a substrate and forming a silicon layer by depositing silicon directly on the polycrystalline silicon seed layer under amorphous process conditions at a temperature below 600 C.Type: GrantFiled: October 25, 2012Date of Patent: April 21, 2015Assignee: Infineon Technologies AGInventors: Wolfgang Lehnert, Stefan Pompl, Markus Meyer
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Publication number: 20140145305Abstract: A method for manufacturing a semiconductor device and a semiconductor device are disclosed. The method comprises forming a trench in a substrate, partially filling the trench with a first semiconductive material, forming an interface along a surface of the first semiconductive material, and filling the trench with a second semiconductive material. The semiconductor device includes a first electrode arranged along sidewalls of a trench and a dielectric arranged over the first electrode. The semiconductor device further includes a second electrode at least partially filling the trench, wherein the second electrode comprises an interface within the second electrode.Type: ApplicationFiled: January 31, 2014Publication date: May 29, 2014Applicant: INFINEON TECHNOLOGIES AGInventors: Wolfgang Lehnert, Michael Stadtmueller, Stefan Pompl, Markus Meyer
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Patent number: 8685828Abstract: A method for manufacturing a semiconductor device and a semiconductor device are disclosed. The method comprises forming a trench in a substrate, partially filling the trench with a first semiconductive material, forming an interface along a surface of the first semiconductive material, and filling the trench with a second semiconductive material. The semiconductor device includes a first electrode arranged along sidewalls of a trench and a dielectric arranged over the first electrode. The semiconductor device further includes a second electrode at least partially filling the trench, wherein the second electrode comprises an interface within the second electrode.Type: GrantFiled: January 14, 2011Date of Patent: April 1, 2014Assignee: Infineon Technologies AGInventors: Wolfgang Lehnert, Michael Stadtmueller, Stefan Pompl, Markus Meyer
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Publication number: 20130221483Abstract: A method of forming a semiconductor device includes forming an opening having a sidewall in a substrate and forming a first epitaxial layer in the opening. The first epitaxial layer is formed in a first portion of the sidewall without growing in a second portion of the sidewall. A second epitaxial layer is formed in the opening after forming the first epitaxial layer. The second epitaxial layer is formed in the second portion of the sidewall. The first epitaxial layer is removed after forming the second epitaxial layer.Type: ApplicationFiled: February 24, 2012Publication date: August 29, 2013Applicant: Infineon Technologies AGInventors: Thomas Popp, Stefan Pompl, Rudolf Berger