Patents by Inventor Stefan Rusu

Stefan Rusu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11808977
    Abstract: Structures and methods for high speed interconnection in photonic systems are described herein. In one embodiment, a photonic device is disclosed. The photonic device includes: a substrate; a plurality of metal layers on the substrate; a photonic material layer comprising graphene over the plurality of metal layers; and an optical routing layer comprising a waveguide on the photonic material layer.
    Type: Grant
    Filed: December 13, 2022
    Date of Patent: November 7, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Weiwei Song, Stefan Rusu, Mohammed Rabiul Islam
  • Publication number: 20230324609
    Abstract: A method includes: determining a first material and a second material of a photonic waveguide for propagating light, the photonic waveguide having a first section and a second section arranged in a first layer and a second layer, respectively, of the photonic waveguide; determining a spacing between the first layer and the second layer; determining a parameter set of a crosstalk reduction structure, according to the spacing, the first material and a wavelength of the light, to cause insertion losses of the first section and the second section to be lower than a predetermined threshold; and forming the first and second sections with the first and second materials, respectively, the first section having the crosstalk reduction structure overlapping the second section.
    Type: Application
    Filed: April 11, 2022
    Publication date: October 12, 2023
    Inventors: MING YANG CHUNG, CHEWN-PU JOU, STEFAN RUSU, CHENG-TSE TANG
  • Publication number: 20230305226
    Abstract: A structure includes an optical interposer attached to a package substrate, wherein the optical interposer includes a silicon waveguide, a first photonic component optically coupled to the silicon waveguide, a second photonic component optically coupled to the silicon waveguide, and an interconnect structure extending over the silicon waveguide, over the first photonic component, and over the second photonic component, wherein the interconnect structure is electrically connected to the first photonic component and to the second photonic component, a first semiconductor device attached to the interconnect structure, wherein the first semiconductor device is electrically connected to the first photonic component through the interconnect structure, and a second semiconductor device attached to the interconnect structure, wherein the second semiconductor device is electrically connected to the second photonic component through the interconnect structure.
    Type: Application
    Filed: June 1, 2023
    Publication date: September 28, 2023
    Inventors: Mohammed Rabiul Islam, Stefan Rusu, Weiwei Song
  • Publication number: 20230308206
    Abstract: An optical device includes a first waveguide, ring-shaped waveguides adjacent to the first waveguide, and heaters coupled to the ring-shaped waveguides in one-to-one correspondence. A method includes coupling a first light source with a first wavelength to the first waveguide, increasing electric current through the heaters until a first one of the ring-shaped waveguides resonates, assigning the first one of the ring-shaped waveguides to the first wavelength, resetting the electric current through the heaters to the initial electric current, coupling a second light source with a second wavelength to the first waveguide wherein the second wavelength is different from the first wavelength, increasing the electric current through the heaters until a second one of the ring-shaped waveguides resonates wherein the second one of the ring-shaped waveguides is different from the first one of the ring-shaped waveguides, and assigning the second one of the ring-shaped waveguides to the second wavelength.
    Type: Application
    Filed: August 16, 2022
    Publication date: September 28, 2023
    Inventors: Chih-Chang Lin, Chan-Hong Chern, Stefan Rusu, Weiwei Song, Lan-Chou Cho
  • Publication number: 20230296846
    Abstract: Disclosed are apparatus and methods for optical coupling.
    Type: Application
    Filed: May 23, 2023
    Publication date: September 21, 2023
    Inventors: Chih-Tsung SHIH, Chewn-pu JOU, Stefan RUSU, Felix Ying-Kit TSUI, Lan-Chou CHO
  • Patent number: 11764766
    Abstract: A flip flop circuit includes a first master portion, a second master portion, at least one determining portion and a slave portion. The first master portion is configured to operate at a first mode and to receive a first input and generate first master outputs. The second master portion is configured to operate at a second mode and to receive a second input and generate second master outputs. The at least one determining portion is configured to receive at least one enable signal, and has determining inputs and determining outputs. The determining inputs are connected to the first master outputs and the second master outputs. The determining portion is configured to determine the determining outputs being the first master outputs or the second master outputs according to the at least one enable signal. The slave portion is configured to receive the determining outputs and generate an output signal.
    Type: Grant
    Filed: January 14, 2021
    Date of Patent: September 19, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Chia Lai, Stefan Rusu
  • Patent number: 11756875
    Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes an insulator layer arranged over a substrate. Further, an upper routing structure is arranged over the insulator layer and is made of a semiconductor material. A lower optical routing structure is arranged below the substrate and is embedded in a lower dielectric structure. The integrated chip further includes an anti-reflective layer that is arranged below the substrate and directly contacts the substrate.
    Type: Grant
    Filed: July 13, 2022
    Date of Patent: September 12, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Weiwei Song, Chan-Hong Chern, Feng-Wei Kuo, Lan-Chou Cho, Stefan Rusu
  • Publication number: 20230280527
    Abstract: An optical device includes an input array, an output array and a waveguide array. The input array is connected to a first slab structure, while the output array is connected to a second slab structure. The waveguide array is optically coupled to the first slab structure and the second slab structure. The waveguide array includes a first connecting part, a second connecting part and a plurality of waveguide channels. The first connecting part is joined with the first slab structure. The second connecting part is joined with the second slab structure, wherein the second connecting part includes a central portion and at least one flank portion, the central portion is connected to and overlapped with the second slab structure, and the at least one flank portion extends over a side surface of the second slab structure. The waveguide channels are joining the first connecting part to the second connecting part.
    Type: Application
    Filed: May 10, 2023
    Publication date: September 7, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Tsung Shih, Felix Yingkit Tsui, Stefan Rusu, Chewn-Pu Jou
  • Publication number: 20230258860
    Abstract: The present disclosure provides a semiconductor device, a photonic circuit, and a method for adjusting a resonant wavelength of an optical modulator. The semiconductor device includes a substrate, a first waveguide disposed on the substrate, and a second waveguide disposed on the substrate and spaced apart from the first waveguide with a first distance. In addition, the second waveguide includes a first electrical coupling portion having a first type doping, a second electrical coupling portion having a second type doping, and an optical coupling portion disposed between the first electrical coupling portion and the second electrical coupling portion, wherein the second waveguide is configured to receive a first voltage through the first electrical coupling portion and the second electrical coupling portion to decrease a resonant wavelength of the second waveguide.
    Type: Application
    Filed: February 17, 2022
    Publication date: August 17, 2023
    Inventors: LAN-CHOU CHO, CHEWN-PU JOU, CHENG-TSE TANG, STEFAN RUSU
  • Publication number: 20230237237
    Abstract: An integrated circuit design method includes receiving an integrated circuit design, and determining a floor plan for the integrated circuit design. The floor plan includes an arrangement of a plurality of functional cells and a plurality of tap cells. Potential latchup locations in the floor plan are determined, and the arrangement of at least one of the functional cells or the tap cells is modified based on the determined potential latchup locations.
    Type: Application
    Filed: March 27, 2023
    Publication date: July 27, 2023
    Inventors: Po-Chia Lai, Kuo-Ji Chen, Wen-Hao Chen, Wun-Jie Lin, Yu-Ti Su, Mohammed Rabiul Islam, Shu-Yi Ying, Stefan Rusu, Kuan-Te Li, David Barry Scott
  • Patent number: 11703639
    Abstract: A structure includes an optical interposer attached to a package substrate, wherein the optical interposer includes a silicon waveguide, a first photonic component optically coupled to the silicon waveguide, a second photonic component optically coupled to the silicon waveguide, and an interconnect structure extending over the silicon waveguide, over the first photonic component, and over the second photonic component, wherein the interconnect structure is electrically connected to the first photonic component and to the second photonic component, a first semiconductor device attached to the interconnect structure, wherein the first semiconductor device is electrically connected to the first photonic component through the interconnect structure, and a second semiconductor device attached to the interconnect structure, wherein the second semiconductor device is electrically connected to the second photonic component through the interconnect structure.
    Type: Grant
    Filed: January 3, 2022
    Date of Patent: July 18, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Mohammed Rabiul Islam, Stefan Rusu, Weiwei Song
  • Patent number: 11704465
    Abstract: An integrated circuit structure includes a first and second power rail extending in a first direction and being located at a first level, a first and second set of conductive structures located at a second level and extending in a second direction, a first and second set of vias, and a first and second conductive structure located at a third level and extending in the second direction. The first set of vias coupling the first power rail to the first set of conductive structures. The second set of vias coupling the second power rail to the second set of conductive structures. The first conductive structure overlaps a first conductive structure of the first set of conductive structures and the second set of conductive structures. The second conductive structure overlaps a second conductive structure of the first set of conductive structures and the second set of conductive structures.
    Type: Grant
    Filed: November 30, 2020
    Date of Patent: July 18, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jung-Chan Yang, Ting-Wei Chiang, Cheng-I Huang, Hui-Zhong Zhuang, Chi-Yu Lu, Stefan Rusu
  • Patent number: 11693186
    Abstract: Disclosed are apparatus and methods for optical coupling. In one example, a described apparatus includes: a planar layer; a grating region comprising an array of scattering elements arranged in the planar layer to form a two-dimensional grating; a first taper structure formed in the planar layer connecting a first side of the grating region to a first waveguide, wherein a shape of the first taper structure is a first triangle that is asymmetric about any line perpendicular to the first side of the grating region in the planar layer; and a second taper structure formed in the planar layer connecting a second side of the grating region to a second waveguide, wherein a shape of the second taper structure is a second triangle that is asymmetric about any line perpendicular to the second side of the grating region in the planar layer, wherein the first side and the second side are substantially perpendicular to each other.
    Type: Grant
    Filed: April 1, 2021
    Date of Patent: July 4, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Tsung Shih, Chewn-Pu Jou, Stefan Rusu, Felix Ying-Kit Tsui, Lan-Chou Cho
  • Patent number: 11686900
    Abstract: An optical device includes an input array, an output array and a waveguide array. The input array is connected to a first slab structure, while the output array is connected to a second slab structure. The waveguide array is optically coupled to the first slab structure and the second slab structure. The waveguide array includes a first connecting part, a second connecting part and a plurality of waveguide channels. The first connecting part is joined with the first slab structure. The second connecting part is joined with the second slab structure, wherein the second connecting part includes a central portion and at least one flank portion, the central portion is connected to and overlapped with the second slab structure, and the at least one flank portion extends over a side surface of the second slab structure. The waveguide channels are joining the first connecting part to the second connecting part.
    Type: Grant
    Filed: March 11, 2021
    Date of Patent: June 27, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Tsung Shih, Felix Yingkit Tsui, Stefan Rusu, Chewn-Pu Jou
  • Patent number: 11651996
    Abstract: A semiconductor device includes first, second, and third metallization layers, on top of one another, that are disposed above a substrate, wherein each of the first, second, and third metallization layer includes a respective metallization structure formed in a respective dielectric layer, wherein the second metallization layer is disposed between the first and third metallization layers; and a via tower structure that extends from the first metallization layer to the third metallization layer so as to electrically couple at least part of the respective metallization structures of the first and third metallization layers.
    Type: Grant
    Filed: February 19, 2021
    Date of Patent: May 16, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Nick Samra, Stefan Rusu
  • Publication number: 20230114059
    Abstract: Structures and methods for high speed interconnection in photonic systems are described herein. In one embodiment, a photonic device is disclosed. The photonic device includes: a substrate; a plurality of metal layers on the substrate; a photonic material layer comprising graphene over the plurality of metal layers; and an optical routing layer comprising a waveguide on the photonic material layer.
    Type: Application
    Filed: December 13, 2022
    Publication date: April 13, 2023
    Inventors: Weiwei SONG, Stefan RUSU, Mohammed Rabiul ISLAM
  • Publication number: 20230105446
    Abstract: Methods of fabricating optical devices with high refractive index materials are disclosed. The method includes forming a first oxide layer on a substrate and forming a patterned template layer with first and second trenches on the first oxide layer. A material of the patterned template layer has a first refractive index. The method further includes forming a first portion of a waveguide and a first portion of an optical coupler within the first and second trenches, respectively, forming a second portion of the waveguide and a second portion of the optical coupler on a top surface of the patterned template layer, and depositing a cladding layer on the second portions of the waveguide and optical coupler. The waveguide and the optical coupler include materials with a second refractive index that is greater than the first refractive index.
    Type: Application
    Filed: December 8, 2022
    Publication date: April 6, 2023
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Weiwei SONG, Chan-Hong CHERN, Chih-Chang LIN, Stefan RUSU, Min-Hsiang HSU
  • Patent number: 11615227
    Abstract: An integrated circuit design method includes receiving an integrated circuit design, and determining a floor plan for the integrated circuit design. The floor plan includes an arrangement of a plurality of functional cells and a plurality of tap cells. Potential latchup locations in the floor plan are determined, and the arrangement of at least one of the functional cells or the tap cells is modified based on the determined potential latchup locations.
    Type: Grant
    Filed: December 21, 2020
    Date of Patent: March 28, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Chia Lai, Kuo-Ji Chen, Wen-Hao Chen, Wun-Jie Lin, Yu-Ti Su, Rabiul Islam, Shu-Yi Ying, Stefan Rusu, Kuan-Te Li, David Barry Scott
  • Publication number: 20230048735
    Abstract: A flip-flop circuit configured to latch an input signal to an output signal is disclosed. The circuit includes a first latch circuit; and a second latch circuit coupled to the first latch circuit. In some embodiments, in response to a clock signal, the first and second latch circuits are complementarily activated so as to latch the input signal to the output signal, and the first and second latch circuits each comprises at most two transistors configured to receive the clock signal.
    Type: Application
    Filed: October 28, 2022
    Publication date: February 16, 2023
    Inventors: Po-Chia LAI, Meng-Hung Shen, Chi-Lin Liu, Stefan Rusu, Yan-Hao Chen, Jerry Chang-Jui Kao
  • Patent number: 11550102
    Abstract: Structures and methods for high speed interconnection in photonic systems are described herein. In one embodiment, a photonic device is disclosed. The photonic device includes: a substrate; a plurality of metal layers on the substrate; a photonic material layer comprising graphene over the plurality of metal layers; and an optical routing layer comprising a waveguide on the photonic material layer.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: January 10, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Weiwei Song, Stefan Rusu, Mohammed Rabiul Islam