Abstract: A microcontroller system includes a higher power reference voltage circuit and a lower power reference voltage circuit configured to draw less power than the higher power reference voltage circuit when enabled. The system includes a power state logic controller configured to enable the lower power reference voltage circuit to provide a first regulated voltage during a power saving mode, and, on exiting the power saving mode, enable the higher power reference voltage circuit to provide a second regulated voltage.

Abstract: A microcontroller system includes a higher power reference voltage circuit and a lower power reference voltage circuit configured to draw less power than the higher power reference voltage circuit when enabled. The system includes a power state logic controller configured to enable the lower power reference voltage circuit to provide a first regulated voltage during a power saving mode, and, on exiting the power saving mode, enable the higher power reference voltage circuit to provide a second regulated voltage.

Abstract: A microcontroller system includes a higher power reference voltage circuit and a lower power reference voltage circuit configured to draw less power than the higher power reference voltage circuit when enabled. The system includes a power state logic controller configured to enable the lower power reference voltage circuit to provide a first regulated voltage during a power saving mode, and, on exiting the power saving mode, enable the higher power reference voltage circuit to provide a second regulated voltage.

Abstract: A microcontroller system includes a main voltage regulator and a low power voltage regulator having a static current consumption less than the static current consumption of the main voltage regulator. A power state controller enables the low power voltage regulator during a power saving mode. On exiting the power saving mode, the power state controller enables the main voltage regulator and disables the low power voltage regulator after determining that the main voltage regulator is ready. The switching circuitry can be asynchronous.

Abstract: A microcontroller system includes a higher power reference voltage circuit and a lower power reference voltage circuit configured to draw less power than the higher power reference voltage circuit when enabled. The system includes a power state logic controller configured to enable the lower power reference voltage circuit to provide a first regulated voltage during a power saving mode, and, on exiting the power saving mode, enable the higher power reference voltage circuit to provide a second regulated voltage.

Abstract: A microcontroller system includes a main voltage regulator and a low power voltage regulator having a static current consumption less than the static current consumption of the main voltage regulator. A power state controller enables the low power voltage regulator during a power saving mode. On exiting the power saving mode, the power state controller enables the main voltage regulator and disables the low power voltage regulator after determining that the main voltage regulator is ready. The switching circuitry can be asynchronous.

Abstract: A laser driver circuit comprising an amplifier device with a plurality of switchable subamplifiers, which can be or are connected to an output for connection of a laser, ith an analog switching device for switching of analog input signals, a plurality of analog inputs for the analog input signals, a plurality of control inputs for receiving digital control signals, wherein each switchable subamplifier has a switching device for switching the amplification by one of the digital control signals, a digital switching device connected to an input of each switching device for the selectable connection of the input of the switching device of each switchable subamplifier to a control input. Whereby each switchable subamplifier has an analog input, which is connected to the analog switching device for the selectable switching of an analog input signal to the analog input.

Abstract: A laser drive circuit and use of digital-to-analog converters is provided, each with a current input and a current output to set current values of partial currents switchable by means of digital channel signals to provide a laser current pulse at least on the basis of a sum of partial currents, wherein at least one current output of one of the digital-to-analog converters is connected to at least one current input of an additional digital-to-analog converter via an analog switch.

Abstract: A device and method for detecting timing of an edge of a signal with respect to a timing of a predefined edge of a periodic signal is provided, wherein the edge defines a state change between a first state and a second state of the signal, and wherein the device can include: a phase-shift element to shift the phase of the signal relative to the phase of the periodic signal by a phase shift value at which the state change can be sensed at a point in time determined by the timing of the predefined edge; and a detection element to detect the timing of the edge relative to the timing of the predefined edge on the basis of the phase shift value. The phase-shift element can be an adjustable delay element for delaying the signal by an adjustable delay value as a phase shift value.

Abstract: A laser driver circuit comprising an amplifier device with a plurality of switchable subamplifiers, which can be or are connected to an output for connection of a laser, ith an analog switching device for switching of analog input signals, a plurality of analog inputs for the analog input signals, a plurality of control inputs for receiving digital control signals, wherein each switchable subamplifier has a switching device for switching the amplification by one of the digital control signals, a digital switching device connected to an input of each switching device for the selectable connection of the input of the switching device of each switchable subamplifier to a control input. Whereby each switchable subamplifier has an analog input, which is connected to the analog switching device for the selectable switching of an analog input signal to the analog input.

Abstract: A laser drive circuit and use of digital-to-analog converters is provided, each with a current input and a current output to set current values of partial currents switchable by means of digital channel signals to provide a laser current pulse at least on the basis of a sum of partial currents, wherein at least one current output of one of the digital-to-analog converters is connected to at least one current input of an additional digital-to-analog converter via an analog switch.

Abstract: A device and method for detecting timing of an edge of a signal with respect to a timing of a predefined edge of a periodic signal is provided, wherein the edge defines a state change between a first state and a second state of the signal, and wherein the device can include: a phase-shift element to shift the phase of the signal relative to the phase of the periodic signal by a phase shift value at which the state change can be sensed at a point in time determined by the timing of the predefined edge; and a detection element to detect the timing of the edge relative to the timing of the predefined edge on the basis of the phase shift value. The phase-shift element can be an adjustable delay element for delaying the signal by an adjustable delay value as a phase shift value.

Abstract: A method for generating a pulse train is provided with adjustable start and end times of individual pulses, in which additional clock signals are generated from a 0th clock signal, the signals which in each case have a frequency of the 0th clock signal and whose phase is shifted in each case relative to a phase of the 0th clock signal. Pairs of one first clock signal and one second clock signal are provided, partial pulses are generated from the properties of the first and second clock signal of a pair in accordance with a timing vector, and the pulse train is generated by superimposition of partial pulses.

Abstract: An amplifier array includes a servo amplifier, which has a reference signal input, a return signal input, and an output signal connection, which supplies an output signal path, a reference signal generator, which supplies reference signals with different level heights to the reference signal input, and with a return, which supplies a signal, attenuated by a value of the feedback attenuation, from the output path as a return signal to the return signal input, whereby the servo amplifier supplies an amplified difference between the reference signal and return signal in the output signal path. The amplifier array has a connectable bypass gain path, which in the connected state is supplied phase-coupled to the reference signal generator and which supplies a bypass output signal in the output path.

Abstract: A frequency divider circuit is disclosed, which has a chain of flip-flops that are connected by a feedback path to a feedback shift register, and has a start circuit that produces a defined initial state of the shift register when the frequency divider circuit is switched on. The start circuit blocks the feedback path for a predetermined length of time following a power up of the frequency divider circuit.

Abstract: An amplifier array includes a servo amplifier, which has a reference signal input, a return signal input, and an output signal connection, which supplies an output signal path, a reference signal generator, which supplies reference signals with different level heights to the reference signal input, and with a return, which supplies a signal, attenuated by a value of the feedback attenuation, from the output path as a return signal to the return signal input, whereby the servo amplifier supplies an amplified difference between the reference signal and return signal in the output signal path. The amplifier array has a connectable bypass gain path, which in the connected state is supplied phase-coupled to the reference signal generator and which supplies a bypass output signal in the output path.

Abstract: A driver circuit that provides a driver pulse sequence with different adjustable driver pulse heights in different time segments is provided. The driver circuit includes n pulse generators that supply pulse height contributions to a summing node, wherein the supplying can be controlled by switching elements individual to the pulse generators, and further includes a control unit that controls at least some of the switching elements as a function of adjustable parameters. The driver circuit also includes a switching matrix with matrix elements, each one of which is associated with a pair having at least one of the time segments and at least one control parameter, and issues a control signal for exactly one switching element of one of the n pulse generators.

Abstract: A method for generating a pulse train is provided with adjustable start and end times of individual pulses, in which additional clock signals are generated from a 0th clock signal, the signals which in each case have a frequency of the 0th clock signal and whose phase is shifted in each case relative to a phase of the 0th clock signal. Pairs of one first clock signal and one second clock signal are provided, partial pulses are generated from the properties of the first and second clock signal of a pair in accordance with a timing vector, and the pulse train is generated by superimposition of partial pulses.

Abstract: A bag manipulating method and assembly including a pair of bag grippers that receive and grip opposing side edges of a bag positioned in a loading station. The bag grippers are movable in a plane substantially normal to a longitudinal axis of the loading station. The bag manipulating assembly also includes upper and lower bag spreader assemblies, each having a suction cup to apply suction to the bag and a spreader plate that is insertable into the bag and movable to spread apart the bag. Preferably, the bag grippers move toward each other in a plane substantially normal to the longitudinal axis while the bag is being spread apart to facilitate opening the bag. To facilitate closing and sealing the bag, the bag grippers move away from each other in a plane substantially normal to the longitudinal axis after the bag has been filled.

Abstract: A method for the asynchronous transmission of data packets in telecommunication networks with a bit rate B is characterized by methoding of the data to be transmitted such that the probability of the occurrence of a 0 or 1 state in the data stream at each bit position is approximately equal and independent of other bit positions (=scrambling); waiting for a guard band time tgb, transmission of a synchronization sequence during time tsy, transmission of a synchronization word during time tco, and transmission of the data payload; detection of a synchronization sequence and synchronization to this in a receiver; detection of the start of the data packet by detection of the synchronization word in the receiver; reception of the data payload in the receiver.