Abstract: A method of forming a semiconductor structure which includes an extremely thin silicon-on-insulator (ETSOI) semiconductor structure having a PFET portion and an NFET portion, a gate structure in the PFET portion and the NFET portion, a high quality nitride spacer adjacent to the gate structures in the PFET portion and the NFET portion and a doped faceted epitaxial silicon germanium raised source/drain (RSD) in the PFET portion. An amorphous silicon layer is formed on the RSD in the PFET portion. A faceted epitaxial silicon RSD is formed on the ETSOI adjacent to the high quality nitride in the NFET portion. The amorphous layer in the PFET portion prevents epitaxial growth in the PFET portion during formation of the RSD in the NFET portion. Extensions are ion implanted into the ETSOI underneath the gate structure in the NFET portion.

Abstract: A method including etching a shallow trench laterally surrounding a portion of a semiconductor substrate, the semiconductor substrate comprising a semiconductor-on-insulator SOI layer, a pad oxide layer, and a pad nitride layer, depositing a first nitride liner, a dielectric liner, and a second nitride liner in the shallow trench, wherein the dielectric liner is located between the first and the second nitride liner, and filling the shallow trench with a shallow trench fill portion.

Abstract: A method for making dual-epi FinFETs is described. The method includes adding a first epitaxial material to an array of fins. The method also includes covering at least a first portion of the array of fins using a first masking material and removing the first epitaxial material from an uncovered portion of the array of fins. Adding a second epitaxial material to the fins in the uncovered portion of the array of fins is included in the method. The method also includes covering a second portion of the array of fins using a second masking material and performing a directional etch using the first masking material and the second masking material. Apparatus and computer program products are also described.

Abstract: A trim part for a body part includes an angled region having diverging limbs that enclose a first angle. A cut-out is disposed in the angled region. A closure part is configured to at least partially close the cut-out and includes diverging limbs that enclose a second angle. At least one of the diverging limbs of the closure part lies in congruence with a respective limb of the angled region so as to form a flush visible side. The first angle of the angled region is greater than the second angle of the closure part and the second limb of the angled region does not lie in congruence with the second limb of the closure part so as to provide a clearance with a third angle.

Abstract: A method for forming an electrical device that includes forming a high-k gate dielectric layer over a semiconductor substrate that is patterned to separate a first portion of the high-k gate dielectric layer that is present on a first conductivity device region from a second portion of the high-k gate dielectric layer that is present on a second conductivity device region. A connecting gate conductor is formed on the first portion and the second portion of the high-k gate dielectric layer. The connecting gate conductor extends from the first conductivity device region over the isolation region to the second conductivity device region. One of the first conductivity device region and the second conductivity device region may then be exposed to an oxygen containing atmosphere. Exposure with the oxygen containing atmosphere modifies a threshold voltage of the semiconductor device that is exposed.

Abstract: A method for making dual-epi FinFETs is described. The method includes adding a first epitaxial material to an array of fins. The method also includes covering at least a first portion of the array of fins using a first masking material and removing the first epitaxial material from an uncovered portion of the array of fins. Adding a second epitaxial material to the fins in the uncovered portion of the array of fins is included in the method. The method also includes covering a second portion of the array of fins using a second masking material and performing a directional etch using the first masking material and the second masking material. Apparatus and computer program products are also described.

Abstract: A shroud element, for example for the engine compartment in the rear region of the vehicle, has a lower support and a thin-walled upper cover. The cover is locally recessed in the longitudinal direction, and rubber strips are provided between the cover and the support in the region of the recesses. The rubber strips also serve as luggage stopping strips and for sound absorption. The support has U-shaped longitudinal grooves locally in formations so that different thermal expansions between the support and the cover can be compensated for.

Abstract: A method for formation of a fin field effect transistor (FinFET) device includes forming a mandrel mask on a metal hardmask layer of a film stack, the film stack including a silicon on insulator (SOI) layer located underneath the metal hardmask layer; forming a large feature (FX) mask on the metal hardmask layer; etching the mandrel mask and the FX mask simultaneously into the metal hardmask layer; etching the mandrel mask and the FX mask into the SOI layer using the etched metal hardmask layer as a mask.

Abstract: A method for formation of a fin field effect transistor (FinFET) device includes forming a mandrel mask and a large feature (FX) mask on a metal hardmask layer of a film stack, the film stack including a silicon on insulator (SOI) layer located underneath the metal hardmask layer; etching the mandrel mask and the FX mask simultaneously into the metal hardmask layer; and etching the mandrel mask and the FX mask into the SOI layer using the etched metal hardmask layer as a mask.

Abstract: A method for making dual-epi FinFETs is described. The method includes adding a first epitaxial material to an array of fins. The method also includes covering at least a first portion of the array of fins using a first masking material and removing the first epitaxial material from an uncovered portion of the array of fins. Adding a second epitaxial material to the fins in the uncovered portion of the array of fins is included in the method. The method also includes covering a second portion of the array of fins using a second masking material and performing a directional etch using the first masking material and the second masking material. Apparatus and computer program products are also described.

Abstract: A thin BOX ETSOI device with robust isolation and method of manufacturing. The method includes providing a wafer with at least a pad layer overlying a first semiconductor layer overlying an oxide layer overlying a second semiconductor layer, wherein the first semiconductor layer has a thickness of 10 nm or less. The process continues with etching a shallow trench into the wafer, extending partially into the second semiconductor layer and forming first spacers on the sidewalls of said shallow trench. After spacer formation, the process continues by etching an area directly below and between the first spacers, exposing the underside of the first spacers, forming second spacers covering all exposed portions of the first spacers, wherein the pad oxide layer is removed, and forming a gate structure over the first semiconductor wafer.

Abstract: Method of forming a semiconductor structure which includes an extremely thin silicon-on-insulator (ETSOI) semiconductor structure having a PFET portion and an NFET portion, a gate structure in the PFET portion and the NFET portion, a high quality nitride spacer adjacent to the gate structures in the PFET portion and the NFET portion and a doped faceted epitaxial silicon germanium raised source/drain (RSD) in the PFET portion. Low quality nitride and high quality nitride are formed on the semiconductor structure. The high quality nitride in the NFET portion is damaged by ion implantation to facilitate its removal. A faceted epitaxial silicon RSD is formed on the ETSOI adjacent to the high quality nitride in the NFET portion. The high quality nitride in the PFET portion is damaged by ion implantation to facilitate its removal. Extensions are ion implanted into the ETSOI underneath the gate structure in the NFET portion.

Abstract: A trim part for a body part includes an angled region having diverging limbs that enclose a first angle. A cut-out is disposed in the angled region. A closure part is configured to at least partially close the cut-out and includes diverging limbs that enclose a second angle. At least one of the diverging limbs of the closure part lies in congruence with a respective limb of the angled region so as to form a flush visible side. The first angle of the angled region is greater than the second angle of the closure part and the second limb of the angled region does not lie in congruence with the second limb of the closure part so as to provide a clearance with a third angle.

Abstract: In an embodiment, a method of fabricating a transistor device comprises: providing a semiconductor topography comprising a gate conductor disposed above a semiconductor substrate between a pair of dielectric spacers; anisotropically etching exposed regions of the semiconductor substrate on opposite sides of the dielectric spacers to form recessed regions in the substrate; oxidizing exposed surfaces of the substrate in the recessed regions to form an oxide thereon; removing the oxide from bottoms of the recessed regions while retaining the oxide upon sidewalls of the recessed regions; and isotropically etching the substrate such that the recessed regions undercut the pair of dielectric spacers.

Abstract: A bumper system for a motor vehicle includes a bumper cross member which is arranged transversely to a travel direction and has two attachment zones for connection to two side rails arranged in parallel relationship to the travel direction. The bumper cross member has a center portion extending between the attachment zones and two end zones to close off the bumper cross member to vehicle sides. A deformation element is arranged behind each of the end zones and constructed to support in the event of a head-on collision with slight overlap the end zone which undergoes a buckling as a result of the head-on collision. At least one belt element at least partly surrounds a circumference of the deformation element and is secured to at least one of the side rails.

Abstract: In a method for producing a motor vehicle bending cross member bending a double-U-profile is initially formed from a metal plank. The double-U-profile has two U-shaped longitudinal sections which are connected by a web. The outer legs of the double-U-profile are longer than the inner legs which are connected by the web.

Abstract: An interior trim part for a bodywork component has a lighting system with a first component that generates a light signal and a second component that outputs the light signal toward the passenger compartment of the motor vehicle. The bodywork component has a moveable region (200) that can be moved with respect to a non-moveable region (300), from a stationary normal position into an open position displaced with respect to the non-moveable region (300). The first component of the light system generates, in the normal position of the moveable region (200), a light signal that is input into the second component which passes on the light signal in the manner of a lightguide.

Abstract: A method for formation of a fin field effect transistor (FinFET) device includes forming a mandrel mask on a metal hardmask layer of a film stack, the film stack including a silicon on insulator (SOI) layer located underneath the metal hardmask layer; forming a large feature (FX) mask on the metal hardmask layer; etching the mandrel mask and the FX mask simultaneously into the metal hardmask layer; etching the mandrel mask and the FX mask into the SOI layer using the etched metal hardmask layer as a mask.

Abstract: A method for formation of a fin field effect transistor (FinFET) device includes forming a mandrel mask and a large feature (FX) mask on a metal hardmask layer of a film stack, the film stack including a silicon on insulator (SOI) layer located underneath the metal hardmask layer; etching the mandrel mask and the FX mask simultaneously into the metal hardmask layer; and etching the mandrel mask and the FX mask into the SOI layer using the etched metal hardmask layer as a mask.

Abstract: A distance-measuring optoelectronic sensor for the monitoring of a working zone is provided which is located within a detection zone of the sensor and at a first distance from the sensor, wherein the sensor has a lighting unit having a light source to illuminate the working zone at least partly as well as an object detection unit by means of which unauthorized objects in the working zone can be detected. In this respect, an illumination control is designed, in a switching-on phase, first to activate the lighting unit with a lower power so that a provisional working zone at a second distance from the sensor less than the first distance is illuminated with at most a preset maximum power; to check by means of the object detection unit whether an unauthorized object intrusion is taking place into the provisional working zone; and if no unauthorized object intrusion is recognized, to activate the lighting unit at a higher power so that the working zone is illuminated with at most the preset maximum power.