Patents by Inventor Stefan Woehlert

Stefan Woehlert has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11410950
    Abstract: A semiconductor substrate has a bond pad. The bond pad includes a layer of an aluminum alloy having a chemical composition including at least 0.3% by weight of at least one of Zn, Mg, Sc, Zr, Ti, Ag and/or Mn, with the balance being at least Al and incidental impurities.
    Type: Grant
    Filed: September 17, 2020
    Date of Patent: August 9, 2022
    Assignee: Infineon Technologies AG
    Inventors: Gert Pfahl, Daniel Bolowski, Marian Sebastian Broll, Michael Kreuz, Evelyn Napetschnig, Holger Schulze, Stefan Woehlert
  • Publication number: 20220093483
    Abstract: A semiconductor device includes a contact metallization layer that includes aluminum and is arranged on a semiconductor substrate, an inorganic passivation structure arranged on the semiconductor substrate, an organic passivation layer comprising a first part that is arranged on the contact metallization layer, and a second part that is arranged on the inorganic passivation structure, a first layer structure including a first part that is in contact with the contact metallization layer, a second part that is contact with the inorganic passivation structure, and a third part that is disposed on the semiconductor substrate laterally between the inorganic passivation structure and the organic passivation layer.
    Type: Application
    Filed: November 30, 2021
    Publication date: March 24, 2022
    Inventors: Jens Peter Konrath, Wolfgang Bergner, Romain Esteve, Richard Gaisberger, Florian Grasse, Jochen Hilsenbeck, Ravi Keshav Joshi, Stefan Kramp, Stefan Krivec, Grzegorz Lupina, Hiroshi Narahashi, Andreas Voerckel, Stefan Woehlert
  • Patent number: 11217500
    Abstract: A semiconductor device includes a contact metallization layer arranged on a semiconductor substrate, an inorganic passivation structure arranged on the semiconductor substrate, and an organic passivation layer. The organic passivation layer is located between the contact metallization layer and the inorganic passivation structure, and located vertically closer to the semiconductor substrate than a part of the organic passivation layer located on top of the inorganic passivation structure.
    Type: Grant
    Filed: April 9, 2019
    Date of Patent: January 4, 2022
    Assignee: Infineon Technologies AG
    Inventors: Jens Peter Konrath, Wolfgang Bergner, Romain Esteve, Richard Gaisberger, Florian Grasse, Jochen Hilsenbeck, Ravi Keshav Joshi, Stefan Kramp, Stefan Krivec, Grzegorz Lupina, Hiroshi Narahashi, Andreas Voerckel, Stefan Woehlert
  • Publication number: 20210265168
    Abstract: A process for producing an electrical contact with a first metal layer and at least one second metal layer on a silicon carbide substrate includes removing at least some of the carbon residue by a cleaning process, to clean the first metal layer. The first metal layer and/or the at least one second metal layer may be generated by sputtering deposition.
    Type: Application
    Filed: May 10, 2021
    Publication date: August 26, 2021
    Inventors: Stefan Krivec, Ronny Kern, Stefan Kramp, Gregor Langer, Hannes Winkler, Stefan Woehlert
  • Patent number: 11043383
    Abstract: A process for producing an electrical contact with a first metal layer and at least one second metal layer on a silicon carbide substrate includes removing at least some of the carbon residue by a chemical cleaning process, to clean the first metal layer. The first metal layer and/or the at least one second metal layer may be generated by sputtering deposition.
    Type: Grant
    Filed: May 24, 2019
    Date of Patent: June 22, 2021
    Assignee: Infineon Technologies AG
    Inventors: Stefan Krivec, Ronny Kern, Stefan Kramp, Gregor Langer, Hannes Winkler, Stefan Woehlert
  • Publication number: 20210091025
    Abstract: A semiconductor substrate has a bond pad. The bond pad includes a layer of an aluminum alloy having a chemical composition including at least 0.3% by weight of at least one of Zn, Mg, Sc, Zr, Ti, Ag and/or Mn, with the balance being at least Al and incidental impurities.
    Type: Application
    Filed: September 17, 2020
    Publication date: March 25, 2021
    Inventors: Gert Pfahl, Daniel Bolowski, Marian Sebastian Broll, Michael Kreuz, Evelyn Napetschnig, Holger Schulze, Stefan Woehlert
  • Publication number: 20200343094
    Abstract: An electronic device, an electronic module comprising the electronic device and methods for fabricating the same are disclosed. In one example, the electronic device includes a semiconductor substrate and a metal stack disposed on the semiconductor substrate, wherein the metal stack comprises a first layer, wherein the first layer comprises NiSi.
    Type: Application
    Filed: July 10, 2020
    Publication date: October 29, 2020
    Applicant: Infineon Technologies AG
    Inventors: Paul Frank, Gretchen Adema, Thomas Bertaud, Michael Ehmann, Eric Graetz, Kamil Karlovsky, Evelyn Napetschnig, Werner Robl, Tobias Schmidt, Joachim Seifert, Frank Wagner, Stefan Woehlert
  • Patent number: 10741402
    Abstract: An electronic device, an electronic module comprising the electronic device and methods for fabricating the same are disclosed. In one example, the electronic device includes a semiconductor substrate and a metal stack disposed on the semiconductor substrate, wherein the metal stack comprises a first layer, wherein the first layer comprises NiSi.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: August 11, 2020
    Assignee: Infineon Technologies AG
    Inventors: Paul Frank, Gretchen Adema, Thomas Bertaud, Michael Ehmann, Eric Graetz, Kamil Karlovsky, Evelyn Napetschnig, Werner Robl, Tobias Schmidt, Joachim Seifert, Frank Wagner, Stefan Woehlert
  • Publication number: 20190362973
    Abstract: A process for producing an electrical contact with a first metal layer and at least one second metal layer on a silicon carbide substrate includes removing at least some of the carbon residue by a chemical cleaning process, to clean the first metal layer. The first metal layer and/or the at least one second metal layer may be generated by sputtering deposition.
    Type: Application
    Filed: May 24, 2019
    Publication date: November 28, 2019
    Inventors: Stefan Krivec, Ronny Kern, Stefan Kramp, Gregor Langer, Hannes Winkler, Stefan Woehlert
  • Patent number: 10446469
    Abstract: A semiconductor device includes a base element and a copper element over the base element. The copper element includes a layer stack having at least two copper layers and at least one intermediate conductive layer of a material different from copper. The at least two copper layers and the at least one intermediate conductive layer are alternately stacked over each other.
    Type: Grant
    Filed: July 22, 2016
    Date of Patent: October 15, 2019
    Assignee: Infineon Technologies AG
    Inventors: Thomas Detzel, Johann Gross, Robert Illing, Maximilian Krug, Sven Gustav Lanzerstorfer, Michael Nelhiebel, Werner Robl, Michael Rogalli, Stefan Woehlert
  • Publication number: 20190311966
    Abstract: A semiconductor device includes a contact metallization layer arranged on a semiconductor substrate, an inorganic passivation structure arranged on the semiconductor substrate, and an organic passivation layer. The organic passivation layer is located between the contact metallization layer and the inorganic passivation structure, and located vertically closer to the semiconductor substrate than a part of the organic passivation layer located on top of the inorganic passivation structure.
    Type: Application
    Filed: April 9, 2019
    Publication date: October 10, 2019
    Inventors: Jens Peter Konrath, Wolfgang Bergner, Romain Esteve, Richard Gaisberger, Florian Grasse, Jochen Hilsenbeck, Ravi Keshav Joshi, Stefan Kramp, Stefan Krivec, Grzegorz Lupina, Hiroshi Narahashi, Andreas Voerckel, Stefan Woehlert
  • Patent number: 9935060
    Abstract: A method for processing a wafer in accordance with various embodiments may include: removing wafer material from an inner portion of the wafer to form a structure at an edge region of the wafer to at least partially surround the inner portion of the wafer, and printing material into the inner portion of the wafer using the structure as a printing mask. A method for processing a wafer in accordance with various embodiments may include: providing a carrier and a wafer, the wafer having a first side and a second side opposite the first side, the first side of the wafer being attached to the carrier, the second side having a structure at an edge region of the wafer, the structure at least partially surrounding an inner portion of the wafer; and printing material onto at least a portion of the second side of the wafer.
    Type: Grant
    Filed: February 13, 2017
    Date of Patent: April 3, 2018
    Assignee: Infineon Technologies AG
    Inventors: Srinivasa Reddy Yeduru, Karl Heinz Gasser, Stefan Woehlert, Karl Mayer, Francisco Javier Santos Rodriguez
  • Publication number: 20180082848
    Abstract: An electronic device, an electronic module comprising the electronic device and methods for fabricating the same are disclosed. In one example, the electronic device includes a semiconductor substrate and a metal stack disposed on the semiconductor substrate, wherein the metal stack comprises a first layer, wherein the first layer comprises NiSi.
    Type: Application
    Filed: August 31, 2017
    Publication date: March 22, 2018
    Applicant: Infineon Technologies AG
    Inventors: Paul Frank, Gretchen Adema, Thomas Bertaud, Michael Ehmann, Eric Graetz, Kamil Karlovsky, Evelyn Napetschnig, Werner Robl, Tobias Schmidt, Joachim Seifert, Frank Wagner, Stefan Woehlert
  • Patent number: 9812376
    Abstract: An electrically conductive element includes an electrically conductive material and a plurality of inclusions of a phase change material. The phase change material has a phase transition temperature Tc between 150° C. and 400° C. The inclusions are separated from each other and are embedded in the electrically conductive material.
    Type: Grant
    Filed: June 29, 2015
    Date of Patent: November 7, 2017
    Assignee: Infineon Technologies AG
    Inventors: Stefan Woehlert, Michael Nelhiebel, Siegfried Roehl
  • Publication number: 20170154857
    Abstract: A method for processing a wafer in accordance with various embodiments may include: removing wafer material from an inner portion of the wafer to form a structure at an edge region of the wafer to at least partially surround the inner portion of the wafer, and printing material into the inner portion of the wafer using the structure as a printing mask. A method for processing a wafer in accordance with various embodiments may include: providing a carrier and a wafer, the wafer having a first side and a second side opposite the first side, the first side of the wafer being attached to the carrier, the second side having a structure at an edge region of the wafer, the structure at least partially surrounding an inner portion of the wafer; and printing material onto at least a portion of the second side of the wafer.
    Type: Application
    Filed: February 13, 2017
    Publication date: June 1, 2017
    Inventors: Srinivasa Reddy Yeduru, Karl Heinz Gasser, Stefan Woehlert, Karl Mayer, Francisco Javier Santos Rodriguez
  • Patent number: 9634108
    Abstract: A method of manufacturing a device comprises depositing one or more metallization layers to a substrate, locally heating an area of the one or more metallization layers to obtain a substrate/metallization-layer compound or a metallization-layer compound, the compound comprising an etch-selectivity toward an etching medium which is different to that of the one or more metallization layers outside the area, and removing the one or more metallization layers in the area or outside the area, depending on the etching selectivity in the area or outside the area, by etching with the etching medium to form the device.
    Type: Grant
    Filed: February 5, 2016
    Date of Patent: April 25, 2017
    Assignee: Infineon Technologies AG
    Inventors: Roland Rupp, Stefan Woehlert, Thomas Gutt, Michael Treu
  • Patent number: 9589880
    Abstract: A method for processing a wafer in accordance with various embodiments may include: removing wafer material from an inner portion of the wafer to form a structure at an edge region of the wafer to at least partially surround the inner portion of the wafer, and printing material into the inner portion of the wafer using the structure as a printing mask. A method for processing a wafer in accordance with various embodiments may include: providing a carrier and a wafer, the wafer having a first side and a second side opposite the first side, the first side of the wafer being attached to the carrier, the second side having a structure at an edge region of the wafer, the structure at least partially surrounding an inner portion of the wafer; and printing material onto at least a portion of the second side of the wafer.
    Type: Grant
    Filed: October 9, 2013
    Date of Patent: March 7, 2017
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Srinivasa Reddy Yeduru, Karl Heinz Gasser, Stefan Woehlert, Karl Mayer, Francisco Javier Santos Rodriguez
  • Publication number: 20170053879
    Abstract: A semiconductor device may include: a substrate; a metallization layer disposed at least one of in or over the substrate; a protection layer disposed at least partially over the metallization layer, wherein the metallization layer includes at least one of: copper, aluminum, gold, silver; and wherein the protection layer includes a nitride material including at least one of: copper, aluminum, gold, silver.
    Type: Application
    Filed: August 21, 2015
    Publication date: February 23, 2017
    Inventors: SRINIVASA REDDY YEDURU, RAINER PELZER, STEFAN WOEHLERT
  • Publication number: 20160329263
    Abstract: A semiconductor device includes a base element and a copper element over the base element. The copper element includes a layer stack having at least two copper layers and at least one intermediate conductive layer of a material different from copper. The at least two copper layers and the at least one intermediate conductive layer are alternately stacked over each other.
    Type: Application
    Filed: July 22, 2016
    Publication date: November 10, 2016
    Inventors: Thomas Detzel, Johann Gross, Robert Illing, Maximilian Krug, Sven Gustav Lanzerstorfer, Michael Nelhiebel, Werner Robl, Michael Rogalli, Stefan Woehlert
  • Patent number: 9418937
    Abstract: An integrated circuit includes a base element and a copper element over the base element, the copper element having a thickness of at least 5 ?m and a ratio of average grain size to thickness of less than 0.7.
    Type: Grant
    Filed: December 9, 2011
    Date of Patent: August 16, 2016
    Assignee: Infineon Technologies AG
    Inventors: Thomas Detzel, Johann Gross, Robert Illing, Maximilian Krug, Sven Gustav Lanzerstorfer, Michael Nelhiebel, Werner Robl, Michael Rogalli, Stefan Woehlert