Patents by Inventor Stefan Woehlert

Stefan Woehlert has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9391154
    Abstract: A method of manufacturing a device comprises depositing one or more metallization layers to a substrate, locally heating an area of the one or more metallization layers to obtain a substrate/metallization-layer compound or a metallization-layer compound, the compound comprising an etch-selectivity toward an etching medium which is different to that of the one or more metallization layers outside the area, and removing the one or more metallization layers in the area or outside the area, depending on the etching selectivity in the area or outside the area, by etching with the etching medium to form the device.
    Type: Grant
    Filed: November 6, 2015
    Date of Patent: July 12, 2016
    Assignee: Infineon Technologies AG
    Inventors: Roland Rupp, Stefan Woehlert, Thomas Gutt, Michael Treu
  • Publication number: 20160155861
    Abstract: A method of manufacturing a device comprises depositing one or more metallization layers to a substrate, locally heating an area of the one or more metallization layers to obtain a substrate/metallization-layer compound or a metallization-layer compound, the compound comprising an etch-selectivity toward an etching medium which is different to that of the one or more metallization layers outside the area, and removing the one or more metallization layers in the area or outside the area, depending on the etching selectivity in the area or outside the area, by etching with the etching medium to form the device.
    Type: Application
    Filed: February 5, 2016
    Publication date: June 2, 2016
    Inventors: Roland Rupp, Stefan Woehlert, Thomas Gutt, Michael Treu
  • Publication number: 20160064504
    Abstract: A method of manufacturing a device comprises depositing one or more metallization layers to a substrate, locally heating an area of the one or more metallization layers to obtain a substrate/metallization-layer compound or a metallization-layer compound, the compound comprising an etch-selectivity toward an etching medium which is different to that of the one or more metallization layers outside the area, and removing the one or more metallization layers in the area or outside the area, depending on the etching selectivity in the area or outside the area, by etching with the etching medium to form the device.
    Type: Application
    Filed: November 6, 2015
    Publication date: March 3, 2016
    Inventors: Roland Rupp, Stefan Woehlert, Thomas Gutt, Michael Treu
  • Publication number: 20160013117
    Abstract: An electrically conductive element includes an electrically conductive material and a plurality of inclusions of a phase change material. The phase change material has a phase transition temperature Tc between 150° C. and 400° C. The inclusions are separated from each other and are embedded in the electrically conductive material.
    Type: Application
    Filed: June 29, 2015
    Publication date: January 14, 2016
    Inventors: Stefan Woehlert, Michael Nelhiebel, Siegfried Roehl
  • Patent number: 9209281
    Abstract: A method of manufacturing a device comprises depositing one or more metallization layers to a substrate, locally heating an area of the one or more metallization layers to obtain a substrate/metallization-layer compound or a metallization-layer compound, the compound comprising an etch-selectivity toward an etching medium which is different to that of the one or more metallization layers outside the area, and removing the one or more metallization layers in the area or outside the area, depending on the etching selectivity in the area or outside the area, by etching with the etching medium to form the device.
    Type: Grant
    Filed: April 23, 2007
    Date of Patent: December 8, 2015
    Assignee: Infineon Technologies AG
    Inventors: Roland Rupp, Stefan Woehlert, Thomas Gutt, Michael Treu
  • Publication number: 20150097294
    Abstract: A method for processing a wafer in accordance with various embodiments may include: removing wafer material from an inner portion of the wafer to form a structure at an edge region of the wafer to at least partially surround the inner portion of the wafer, and printing material into the inner portion of the wafer using the structure as a printing mask. A method for processing a wafer in accordance with various embodiments may include: providing a carrier and a wafer, the wafer having a first side and a second side opposite the first side, the first side of the wafer being attached to the carrier, the second side having a structure at an edge region of the wafer, the structure at least partially surrounding an inner portion of the wafer; and printing material onto at least a portion of the second side of the wafer.
    Type: Application
    Filed: October 9, 2013
    Publication date: April 9, 2015
    Applicant: Infineon Technologies AG
    Inventors: Srinivasa Reddy Yeduru, Karl Heinz Gasser, Stefan Woehlert, Karl Mayer, Francisco Javier Santos Rodriguez
  • Patent number: 8502274
    Abstract: Power transistor cells are formed in a cell array of an integrated circuit. Contact vias may electrically connect a metal structure above the cell array and the power transistor cells. A connecting line electrically connects a first element arranged in the cell array and a second element arranged in a peripheral region. A portion of the connecting line is arranged between the metal structure and the cell array and runs between a first axis and a second axis which are arranged parallel and at a distance to each other. The distance is greater than a width of the connecting line portion. The connecting line portion is tangent to both the first axis and the second axis. Shear-induced material transport along the connecting line is reduced by shortening critical portions or by exploiting grain boundary effects. The reliability of an insulator structure covering the connecting line is increased.
    Type: Grant
    Filed: April 6, 2012
    Date of Patent: August 6, 2013
    Assignee: Infineon Technologies AG
    Inventors: Kurt Matoy, Thomas Detzel, Michael Nelhiebel, Arno Zechmann, Stefan Decker, Robert Illing, Sven Gustav Lanzerstorfer, Christian Djelassi, Bernhard Auer, Stefan Woehlert
  • Publication number: 20130147047
    Abstract: An integrated circuit includes a base element and a copper element over the base element, the copper element having a thickness of at least 5 ?m and a ratio of average grain size to thickness of less than 0.7.
    Type: Application
    Filed: December 9, 2011
    Publication date: June 13, 2013
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Thomas Detzel, Johann Gross, Robert Illing, Maximilian Krug, Sven Gustav Lanzerstorfer, Michael Nelhiebel, Werner Robl, Michael Rogalli, Stefan Woehlert
  • Patent number: 8324115
    Abstract: A semiconductor chip (1) is provided having an adhesion-promoting-layer-free three-layer metallization (2). The three-layer metallization (2) has an aluminum layer (4) applied directly on the semiconductor chip (1), a diffusion barrier layer (5) applied directly on the aluminum layer (4), and a solder layer (6) applied directly on the diffusion barrier layer (5). Ti, Ni, Pt or Cr is provided as the diffusion barrier layer (5) and a diffusion solder layer is provided as the solder layer (6). All three layers are applied by sputtering in a process sequence.
    Type: Grant
    Filed: November 2, 2006
    Date of Patent: December 4, 2012
    Assignee: Infineon Technologies AG
    Inventors: Ralf Otremba, Daniel Kraft, Alexander Komposch, Hannes Eder, Paul Ganitzer, Stefan Woehlert
  • Patent number: 8156643
    Abstract: A method of electrically interconnecting a semiconductor chip to another electronic device including providing a carrier including contact pins and a chip attached to the carrier, the chip having a copper contact pad that faces away from the carrier, extending a copper electrical connector between the contact pins and the contact pad, and diffusion soldering the copper electrical connector to the active area with a solder material including tin to form a solder connection including a contiguous bronze coating disposed between and in direct contact with both the copper electrical connector and the contact pad.
    Type: Grant
    Filed: January 19, 2011
    Date of Patent: April 17, 2012
    Assignee: Infineon Technologies AG
    Inventors: Manfred Schneegans, Markus Leicht, Stefan Woehlert, Edmund Riedl
  • Patent number: 8097918
    Abstract: A semiconductor arrangement including a load transistor and a sense transistor that are integrated in a semiconductor body. One embodiment provides a number of transistor cells integrated in the semiconductor body, each transistor cell including a first active transistor region. A number of first contact electrodes, each of the contact electrodes contacting the first active transistor regions through contact plugs. A second contact electrode contacts a first group of the first contact electrodes, but not contacting a second group of the first contact electrodes. The transistor cells being contacted by first contact electrodes of the first group form a load transistor, with the second electrode forming a load terminal of the load transistor. The transistor cells being contacted by first contact electrodes of the second group form a sense transistor.
    Type: Grant
    Filed: August 14, 2009
    Date of Patent: January 17, 2012
    Assignee: Infineon Technologies AG
    Inventors: Christoph Kadow, Markus Leicht, Stefan Woehlert
  • Publication number: 20110107595
    Abstract: A method of electrically interconnecting a semiconductor chip to another electronic device including providing a carrier including contact pins and a chip attached to the carrier, the chip having a copper contact pad that faces away from the carrier, extending a copper electrical connector between the contact pins and the contact pad, and diffusion soldering the copper electrical connector to the active area with a solder material including tin to form a solder connection including a contiguous bronze coating disposed between and in direct contact with both the copper electrical connector and the contact pad.
    Type: Application
    Filed: January 19, 2011
    Publication date: May 12, 2011
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Manfred Schneegans, Markus Leicht, Stefan Woehlert, Edmund Riedl
  • Publication number: 20110037126
    Abstract: A semiconductor arrangement including a load transistor and a sense transistor that are integrated in a semiconductor body. One embodiment provides a number of transistor cells integrated in the semiconductor body, each transistor cell including a first active transistor region. A number of first contact electrodes, each of the contact electrodes contacting the first active transistor regions through contact plugs. A second contact electrode contacts a first group of the first contact electrodes, but not contacting a second group of the first contact electrodes. The transistor cells being contacted by first contact electrodes of the first group form a load transistor, with the second electrode forming a load terminal of the load transistor. The transistor cells being contacted by first contact electrodes of the second group form a sense transistor.
    Type: Application
    Filed: August 14, 2009
    Publication date: February 17, 2011
    Applicant: Infineon Technologies AG
    Inventors: Christoph Kadow, Markus Leicht, Stefan Woehlert
  • Patent number: 7834427
    Abstract: An integrated circuit including a semiconductor arrangement, a power semiconductor component and an associated production method is disclosed. One embodiment includes a carrier substrate, a first interconnect layer, formed on the carrier substrate and has at least one cutout, an insulating filling layer, formed on the first interconnect layer and the carrier substrate and fills at least one cutout, an SiON layer, formed on the filling layer, and a second interconnect layer, formed over the SiON layer.
    Type: Grant
    Filed: February 28, 2007
    Date of Patent: November 16, 2010
    Assignee: Infineon Technologies Austria AG
    Inventors: Thomas Detzel, Hubert Maier, Kai-Alexander Schreiber, Stefan Woehlert, Uwe Hoeckele
  • Publication number: 20080315423
    Abstract: A semiconductor device includes a carrier, a chip including a first face having a contact area, where the chip is attached to the carrier such that the contact area faces away from the carrier, a copper connector configured for attachment to the contact area, and a solder material configured to couple the copper connector to the contact area.
    Type: Application
    Filed: June 25, 2007
    Publication date: December 25, 2008
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Manfred Schneegans, Markus Leicht, Stefan Woehlert, Edmund Riedl
  • Publication number: 20080258183
    Abstract: A method of manufacturing a device comprises depositing one or more metallization layers to a substrate, locally heating an area of the one or more metallization layers to obtain a substrate/metallization-layer compound or a metallization-layer compound, the compound comprising an etch-selectivity toward an etching medium which is different to that of the one or more metallization layers outside the area, and removing the one or more metallization layers in the area or outside the area, depending on the etching selectivity in the area or outside the area, by etching with the etching medium to form the device.
    Type: Application
    Filed: April 23, 2007
    Publication date: October 23, 2008
    Applicant: Infineon Technologies AG
    Inventors: Roland Rupp, Stefan Woehlert, Thomas Gutt, Michael Treu
  • Publication number: 20080179669
    Abstract: An integrated circuit including a semiconductor arrangement, a power semiconductor component and an associated production method is disclosed. One embodiment includes a carrier substrate, a first interconnect layer, formed on the carrier substrate and has at least one cutout, an insulating filling layer, formed on the first interconnect layer and the carrier substrate and fills at least one cutout, an SiON layer, formed on the filling layer, and a second interconnect layer, formed over the SiON layer.
    Type: Application
    Filed: February 28, 2007
    Publication date: July 31, 2008
    Applicant: INFINEON TECHNOLOGIES AUSTRIA AG
    Inventors: Thomas Detzel, Hubert Maier, Kai-Alexander Schreiber, Stefan Woehlert, Uwe Hoeckele
  • Publication number: 20080105907
    Abstract: A semiconductor chip (1) is provided having an adhesion-promoting-layer-free three-layer metallization (2). The three-layer metallization (2) has an aluminum layer (4) applied directly on the semiconductor chip (1), a diffusion barrier layer (5) applied directly on the aluminum layer (4), and a solder layer (6) applied directly on the diffusion barrier layer (5). Ti, Ni, Pt or Cr is provided as the diffusion barrier layer (5) and a diffusion solder layer is provided as the solder layer (6). All three layers are applied by sputtering in a process sequence.
    Type: Application
    Filed: November 2, 2006
    Publication date: May 8, 2008
    Inventors: Ralf Otremba, Daniel Kraft, Alexander Komposch, Hannes Eder, Paul Ganitzer, Stefan Woehlert
  • Publication number: 20060273810
    Abstract: A silicon wafer with a solderable coating on its wafer rear side and a process for producing it is disclosed. The silicon wafer has integrated circuits on its wafer top side. The rear side coating is free of silver constituents in the immediate vicinity of an adapted gold coating on which a gold/tin solder material is arranged, the volume of gold in the adapted gold coating, together with the volume of gold in the solder material in relation to the volume of tin in the solder material corresponding to the eutectic melt system comprising gold and tin in thermodynamic equilibrium.
    Type: Application
    Filed: May 24, 2006
    Publication date: December 7, 2006
    Inventors: Paul Ganitzer, Stefan Woehlert