Patents by Inventor Stefano S. Oggioni

Stefano S. Oggioni has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9698089
    Abstract: An electronic circuit includes a substrate device which includes a first substrate section including a first plurality of layers attached to each other having a first orientation (x2) and a second substrate section including a second plurality of layers attached to each other. The second plurality of layers have a second orientation (x3). The first orientation (x2) and the second orientation (x3) are perpendicular with respect to one another.
    Type: Grant
    Filed: June 24, 2016
    Date of Patent: July 4, 2017
    Assignee: International Business Machines Corporation
    Inventors: Thomas J. Brunschwiler, Dominic Gschwend, Keiji Matsumoto, Stefano S. Oggioni, Gerd Schlottig, Timo J. Tick, Jonas Zuercher
  • Patent number: 9673179
    Abstract: The invention relates to a method for embedding a discrete electronic device in a chip module. The chip module comprises a multilayer substrate which comprises a plurality of electrically conductive layers stacked above each other and an electrically non-conductive layer arranged between each pair of electrically conductive layers. The chip module is configured to receive one or more chips to be mounted onto a top surface thereof. Each electrically conductive layer comprises one or more electrically conductive structures. A recess is provided in a side surface of the chip module. The discrete electronic device is inserted into the recess. A first electrically conductive connection between a first electrical contact of the discrete electronic device and a first electrically conductive structure is established. Further, a second electrically conductive connection between a second electrical contact of the discrete electronic device and a second electrically conductive structure is established.
    Type: Grant
    Filed: July 20, 2016
    Date of Patent: June 6, 2017
    Assignee: International Business Machines Corporation
    Inventors: Andreas Huber, Harald Huels, Stefano S. Oggioni, Thomas Strach, Thomas-Michael Winkel
  • Publication number: 20170118839
    Abstract: The present invention is notably directed to a printed circuit board, or PCB. This PCB has two main surfaces, each delimited by lateral edges, as well as lateral surfaces, each meeting each of the two main surfaces at one lateral edge. The present PCB further comprises a row of solder pads, which extends along a lateral edge of the PCB. Each solder pad is formed directly at the lateral edge and/or directly on a lateral surface (meeting one of the two main surfaces at said lateral edge). I.e., each pad interrupts a lateral edge and/or an adjoining lateral surface. One or more chips, e.g., memory chips, can be mounted on such a PCB to form an IC package. The above solder pad arrangement allows particularly dense arrangements of IC packages to be obtained. The present invention is further directed to related devices and methods of fabrication thereof.
    Type: Application
    Filed: October 23, 2015
    Publication date: April 27, 2017
    Inventors: Thomas Brunschwiler, Andreas Doering, Ronald P. Luijten, Stefano S. Oggioni, Joerg-Eric Sagmeister, Patricia Sagmeister, Martin Schmatz
  • Publication number: 20170094808
    Abstract: Methods of fabricating electronic circuits and electronic packages are provided. The electronic circuit includes a multilayer circuit board, and a tamper-respondent sensor embedded within the circuit board. The tamper-respondent sensor defines, at least in part, a secure volume associated with the multilayer circuit board. In certain implementations, the tamper-respondent sensor includes multiple tamper-respondent layers embedded within the circuit board including, for instance, one or more tamper-respondent frames and one or more tamper-respondent mat layers, with the tamper-respondent frame(s) being disposed, at least in part, above the tamper-respondent mat layer(s), which together define the secure volume where extending into the multilayer circuit board.
    Type: Application
    Filed: November 16, 2015
    Publication date: March 30, 2017
    Inventors: William L. BRODSKY, Silvio DRAGONE, Roger S. KRABBENHOFT, David C. LONG, Stefano S. OGGIONI, Michael T. PEETS, William SANTIAGO-FERNANDEZ
  • Publication number: 20170089729
    Abstract: Electronic circuits, electronic packages, and methods of fabrication are provided. The electronic circuit includes a multilayer circuit board, and a tamper-respondent sensor embedded within the circuit board. The tamper-respondent sensor defines, at least in part, a secure volume associated with the multilayer circuit board. In certain implementations, the tamper-respondent sensor includes multiple tamper-respondent layers embedded within the circuit board including, for instance, one or more tamper-respondent frames and one or more tamper-respondent mat layers, with the tamper-respondent frame(s) being disposed, at least in part, above the tamper-respondent mat layer(s), which together define the secure volume where extending into the multilayer circuit board.
    Type: Application
    Filed: September 25, 2015
    Publication date: March 30, 2017
    Inventors: William L. BRODSKY, Silvio DRAGONE, Roger S. KRABBENHOFT, David C. LONG, Stefano S. OGGIONI, Michael T. PEETS, William SANTIAGO-FERNANDEZ
  • Publication number: 20170020003
    Abstract: A circuitized structure with a 3-dimensional configuration. A base structure is provided that includes an insulating substrate of electrically insulating material with a flat configuration, and further includes an electric circuit including at least one layer of electrically conductive material arranged on the insulating substrate. The insulating material includes a thermosetting material being partially cured by stopping a cure thereof at a B-stage before reaching a gel point. The base structure is formed according to the 3-dimensional configuration, and the cure of the thermosetting material is completed.
    Type: Application
    Filed: June 28, 2016
    Publication date: January 19, 2017
    Inventors: Silvio Dragone, Stefano S. Oggioni, William Santiago Fernandez
  • Publication number: 20170019987
    Abstract: A circuitized structure with a 3-dimensional configuration. A base structure is provided that includes an insulating substrate of electrically insulating material with a flat configuration, and further includes an electric circuit including at least one layer of electrically conductive material arranged on the insulating substrate. The insulating material includes a thermosetting material being partially cured by stopping a cure thereof at a B-stage before reaching a gel point. The base structure is formed according to the 3-dimensional configuration, and the cure of the thermosetting material is completed.
    Type: Application
    Filed: July 15, 2015
    Publication date: January 19, 2017
    Inventors: Silvio Dragone, Stefano S. Oggioni, William Santiago Fernandez
  • Publication number: 20160351485
    Abstract: An electronic circuit includes a substrate device which includes a first substrate section including a first plurality of layers attached to each other having a first orientation (x2) and a second substrate section including a second plurality of layers attached to each other. The second plurality of layers have a second orientation (x3). The first orientation (x2) and the second orientation (x3) are perpendicular with respect to one another.
    Type: Application
    Filed: June 24, 2016
    Publication date: December 1, 2016
    Inventors: Thomas J. Brunschwiler, Dominic Gschwend, Keiji Matsumoto, Stefano S. Oggioni, Gerd Schlottig, Timo J. Tick, Jonas Zuercher
  • Patent number: 9433077
    Abstract: A substrate device for electronic circuits or devices includes a first substrate section including a first plurality of layers attached to each other having a first orientation (x2) and a second substrate section including a second plurality of layers attached to each other. The second plurality of layers have a second orientation (x3). The first orientation (x2) and the second orientation (x3) are angled (?) with respect to one another.
    Type: Grant
    Filed: January 19, 2015
    Date of Patent: August 30, 2016
    Assignee: International Business Machines Corporation
    Inventors: Thomas J. Brunschwiler, Dominic Gschwend, Keiji Matsumoto, Stefano S. Oggioni, Gerd Schlottig, Timo J. Tick, Jonas Zuercher
  • Publication number: 20160061365
    Abstract: An embodiment of the invention may include a sealing apparatus. The sealing apparatus may include a first component having a body, where the body has an outer surface and a first arm protruding from the outer surface. The first arm includes an inner surface facing the outer surface of the body. The sealing apparatus may include a second component engaged by the first arm of the first component. The second component may have a first portion arranged inside a space between the inner surface of the first arm and the outer surface of the body and a second portion arranged outside of the space and adjacent to an outer surface of the first arm.
    Type: Application
    Filed: August 19, 2015
    Publication date: March 3, 2016
    Inventors: Ingmar G. Meijer, Stefano S. Oggioni, Stephan Paredes, Gerd Schlottig
  • Publication number: 20150237729
    Abstract: A substrate device for electronic circuits or devices includes a first substrate section including a first plurality of layers attached to each other having a first orientation (x2) and a second substrate section including a second plurality of layers attached to each other. The second plurality of layers have a second orientation (x3). The first orientation (x2) and the second orientation (x3) are angled (?) with respect to one another.
    Type: Application
    Filed: January 19, 2015
    Publication date: August 20, 2015
    Inventors: Thomas J. Brunschwiler, Dominic Gschwend, Keiji Matsumoto, Stefano S. Oggioni, Gerd Schlottig, Timo J. Tick, Jonas Zuercher
  • Patent number: 9055701
    Abstract: An improved alignment precision of Micro-Electromechanical Systems (MEMS). A method includes two parts of MEMS separated by at least one rolling element having a first diameter, where the rolling element is maintained on one of the two parts using a thermally dissipative material, horizontally aligning the two parts by pivoting one of the two parts about the rolling element, and locking the two parts together.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: June 9, 2015
    Assignee: International Business Machines Corporation
    Inventors: Stefano S. Oggioni, Michel Despont, Mark Lantz, Thomas Albrecht
  • Patent number: 8938627
    Abstract: An arrangement for the protection of cryptographic keys and codes from being compromised by external tampering, wherein the arrangement is utilized within a multilayered securing structure. More particularly, there is provided a multilayered securing structure for the protection of cryptographic keys and codes, which may be subject to potential tampering when employed in computers and/or telecommunication systems. A method is provided for producing such multilayered securing structures within a modular substrate with the intent to protect cryptographic keys and codes which are employed in computers and/or telecommunication systems from the dangers of potential tampering or unauthorized access.
    Type: Grant
    Filed: April 13, 2010
    Date of Patent: January 20, 2015
    Assignee: International Business Machines Corporation
    Inventors: Stefano S. Oggioni, Vincenzo Condorelli, Claudius Feger
  • Patent number: 8907503
    Abstract: A method for manufacturing an underfill in a semiconductor chip stack having a cavity between a first surface and a second surface includes providing at least one access hole in one of the first or second surface; providing at least one vent hole in the one of the first or second surfaces; and applying a viscous filling material through the at least one access hole into the cavity thereby squeezing out air or gas through the at least one vent hole.
    Type: Grant
    Filed: July 17, 2013
    Date of Patent: December 9, 2014
    Assignee: International Business Machines Corporation
    Inventors: Thomas J. Brunschwiler, Javier V. Goicochea, Stefano S. Oggioni, Gerd Schlottig
  • Patent number: 8752284
    Abstract: A method of producing a land grid array (LGA) interposer structure, including an electrically insulating carrier plane, and at least one interposer mounted on a first surface of said carrier plane. The interposer possesses a hemi-toroidal configuration in transverse cross-section and is constituted of a dielectric elastomeric material. A plurality of electrically-conductive elements are arranged about the surface of the at least one hemi-toroidal interposer and extend radically inwardly and downwardly from an uppermost end thereof into electrical contact with at least one component located on an opposite side of the electrically insulating carrier plane.
    Type: Grant
    Filed: March 13, 2008
    Date of Patent: June 17, 2014
    Assignee: International Business Machines Corporation
    Inventors: Gareth G. Hougham, Brian S. Beaman, Evan G. Colgan, Paul W. Coteus, Stefano S. Oggioni, Enrique Vargas
  • Patent number: 8707553
    Abstract: A method and system for improving alignment precision of a pair of MEMS parts. The method involves stacking the two parts such that at least one rolling element is between facing surfaces of said two parts, and each rolling element has a first diameter and an axis of rotation parallel to the facing surfaces. The first and second of a pair of MEMS parts respectively include a first alignment pad and a second alignment pad and a liquid drop formed in contact with both alignment pads can align the two parts which can then be locked together by solidification of solder while remaining spaced by the first diameter.
    Type: Grant
    Filed: May 17, 2005
    Date of Patent: April 29, 2014
    Assignee: International Business Machines Corporation
    Inventors: Stefano S. Oggioni, Michel Despont, Mark Lantz, Thomas Albrecht
  • Publication number: 20140027932
    Abstract: A method for manufacturing an underfill in a semiconductor chip stack having a cavity between a first surface and a second surface includes providing at least one access hole in one of the first or second surface; providing at least one vent hole in the one of the first or second surfaces; and applying a viscous filling material through the at least one access hole into the cavity thereby squeezing out air or gas through the at least one vent hole.
    Type: Application
    Filed: July 17, 2013
    Publication date: January 30, 2014
    Inventors: Thomas J. Brunschwiler, Javier V. Goicochea, Stefano S. Oggioni, Gerd Schlottig
  • Patent number: 8505200
    Abstract: A method of producing a module arrangement which includes a land grid array (LGA) interposer structure, including an electrically insulating carrier plane, and at least one interposer mounted on a first surface of said carrier plane. The interposer possesses a hemi-toroidal configuration in transverse cross-section and is constituted of a dielectric elastomeric material. A plurality of electrically-conductive elements are arranged about the surface of the at least one hemi-toroidal interposer and extend radically inwardly and downwardly from an uppermost end thereof into electrical contact with at least one component located on an opposite side of the electrically insulating carrier plane.
    Type: Grant
    Filed: September 11, 2008
    Date of Patent: August 13, 2013
    Assignee: International Business Machines Corporation
    Inventors: Gareth G. Hougham, Brian S. Beaman, Evan G. Colgan, Paul W. Coteus, Stefano S. Oggioni, Enrique Vargas
  • Patent number: 8479388
    Abstract: A method of producing a land grid array (LGA) interposer structure, including an electrically insulating carrier plane, and at least one interposer mounted on a first surface of said carrier plane. The interposer possesses a hemi-toroidal configuration in transverse cross-section and is constituted of a dielectric elastomeric material. A plurality of electrically-conductive elements are arranged about the surface of the at least one hemi-toroidal interposer and extend radically inwardly and downwardly from an uppermost end thereof into electrical contact with at least one component located on an opposite side of the electrically insulating carrier plane.
    Type: Grant
    Filed: September 10, 2008
    Date of Patent: July 9, 2013
    Assignee: International Business Machines Corporation
    Inventors: Gareth G. Hougham, Brian S. Beaman, Evan G. Colgan, Paul W. Coteus, Stefano S. Oggioni, Enrique Vargas
  • Patent number: 8355259
    Abstract: Substrates are connected by demountable coupling by connecting an electronic module to a substrate. An electronic module and a substrate carrying electrical and/or optical circuits are provided. A connector electrical circuit is connected between the substrate and the electronic module. The connector electrical circuit is electrically demountable dry connected to the electronic module.
    Type: Grant
    Filed: December 4, 2009
    Date of Patent: January 15, 2013
    Assignee: International Business Machines Corporation
    Inventors: Christoph Berger, Laurent Dellmann, Stefano S. Oggioni