Patents by Inventor Steffen Thiel

Steffen Thiel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250171553
    Abstract: Single domain antibodies are provided, which are capable of specifically binding to an epitope of a human complement factor selected from the group consisting of C1q, C3, C4 and/or the proteolytic derivatives C3b and C4b. Further the use of the antibodies are provided for methods in modulating the activity of the complement system as well as methods of treating disorders associated with complement activation.
    Type: Application
    Filed: February 5, 2025
    Publication date: May 29, 2025
    Inventors: Nick Stub Laursen, Dennis Vestergaard Pedersen, Gregers Rom Andersen, Steffen Thiel, Alessandra Zarantonello, Rasmus Kjeldsen Jensen, Henrik Pedersen
  • Publication number: 20250171554
    Abstract: Single domain antibodies are provided, which are capable of specifically binding to an epitope of a human complement factor selected from the group consisting of C1q, C3, C4 and/or the proteolytic derivatives C3b and C4b. Further the use of the antibodies are provided for methods in modulating the activity of the complement system as well as methods of treating disorders associated with complement activation.
    Type: Application
    Filed: February 5, 2025
    Publication date: May 29, 2025
    Inventors: Nick Stub Laursen, Dennis Vestergaard Pedersen, Gregers Rom Andersen, Steffen Thiel, Alessandra Zarantonello, Rasmus Kjeldsen Jensen, Henrik Pedersen
  • Patent number: 12258416
    Abstract: Single domain antibodies are provided, which are capable of specifically binding to an epitope of a human complement factor selected from the group consisting of C1q, C3, C4 and/or the proteolytic derivatives C3b and C4b. Further the use of the antibodies are provided for methods in modulating the activity of the complement system as well as methods of treating disorders associated with complement activation.
    Type: Grant
    Filed: March 27, 2024
    Date of Patent: March 25, 2025
    Assignee: Aarhus Universitet
    Inventors: Nick Stub Laursen, Dennis Vestergaard Pedersen, Gregers Rom Andersen, Steffen Thiel, Alessandra Zarantonello, Rasmus Kjeldsen Jensen, Henrik Pedersen
  • Patent number: 12240912
    Abstract: Single domain antibodies are provided, which are capable of specifically binding to an epitope of a human complement factor selected from the group consisting of C1q, C3, C4 and/or the proteolytic derivatives C3b and C4b. Further the use of the antibodies are provided for methods in modulating the activity of the complement system as well as methods of treating disorders associated with complement activation.
    Type: Grant
    Filed: March 27, 2024
    Date of Patent: March 4, 2025
    Assignee: Aarhus Universitet
    Inventors: Nick Stub Laursen, Dennis Vestergaard Pedersen, Gregers Rom Andersen, Steffen Thiel, Alessandra Zarantonello, Rasmus Kjeldsen Jensen, Henrik Pedersen
  • Patent number: 12110321
    Abstract: Single domain antibodies are provided, which are capable of specifically binding to an epitope of a human complement factor selected from the group consisting of C1q, C3, C4 and/or the proteolytic derivatives C3b and C4b. Further the use of the antibodies are provided for methods in modulating the activity of the complement system as well 5 as methods of treating disorders associated with complement activation.
    Type: Grant
    Filed: June 11, 2019
    Date of Patent: October 8, 2024
    Assignee: Aarhus Universitet
    Inventors: Nick Stub Laursen, Dennis Vestergaard Pedersen, Gregers Rom Andersen, Steffen Thiel, Alessandra Zarantonello, Rasmus Kjeldsen Jensen, Henrik Pedersen
  • Publication number: 20230017307
    Abstract: A driver device includes: a voltage terminal; a ground terminal; an output terminal; a first nMOS power transistor having a drain electrically connected to the voltage terminal, a source electrically connected to the output terminal, and a gate; an overvoltage protection circuit configured to limit a gate-to-source voltage of the first nMOS power transistor in a normal operating mode for the driver device; a pulldown circuit configured to force the first nMOS power transistor off in a stress test mode for the driver device; and a blocking circuit configured to block current flow from the output terminal to the ground terminal through the overvoltage protection circuit and the pulldown circuit in the stress test mode. A method of stress testing the driver device is also described.
    Type: Application
    Filed: July 16, 2021
    Publication date: January 19, 2023
    Inventors: Carmelo Giunta, Marcus Nuebling, Steffen Thiele
  • Patent number: 11549998
    Abstract: A driver device includes: a voltage terminal; a ground terminal; an output terminal; a first nMOS power transistor having a drain electrically connected to the voltage terminal, a source electrically connected to the output terminal, and a gate; an overvoltage protection circuit configured to limit a gate-to-source voltage of the first nMOS power transistor in a normal operating mode for the driver device; a pulldown circuit configured to force the first nMOS power transistor off in a stress test mode for the driver device; and a blocking circuit configured to block current flow from the output terminal to the ground terminal through the overvoltage protection circuit and the pulldown circuit in the stress test mode. A method of stress testing the driver device is also described.
    Type: Grant
    Filed: July 16, 2021
    Date of Patent: January 10, 2023
    Assignee: Infineon Technologies AG
    Inventors: Carmelo Giunta, Marcus Nuebling, Steffen Thiele
  • Publication number: 20210253682
    Abstract: Single domain antibodies are provided, which are capable of specifically binding to an epitope of a human complement factor selected from the group consisting of C1q, C3, C4 and/or the proteolytic derivatives C3b and C4b. Further the use of the antibodies are provided for methods in modulating the activity of the complement system as well 5 as methods of treating disorders associated with complement activation.
    Type: Application
    Filed: June 11, 2019
    Publication date: August 19, 2021
    Applicant: Aarhus Universitet
    Inventors: Nick Stub Laursen, Dennis Vestergaard Pedersen, Gregers Rom Andersen, Steffen Thiel, Alessandra Zarantonello, Rasmus Kjeldsen Jensen, Henrik Pedersen
  • Patent number: 10950509
    Abstract: A semiconductor device includes a first chip pad, a power semiconductor chip arranged on the first chip pad and including at least a first and a second power electrode, and a clip connected to the first power electrode. In this case, an integral part of the clip forms a shunt resistor and a first contact finger of the shunt resistor is embodied integrally with the clip.
    Type: Grant
    Filed: April 30, 2019
    Date of Patent: March 16, 2021
    Assignee: Infineon Technologies AG
    Inventors: Rainald Sander, Thomas Bemmerl, Steffen Thiele
  • Publication number: 20190348333
    Abstract: A semiconductor device comprises a first chip pad, a power semiconductor chip arranged on the first chip pad and comprising at least a first and a second power electrode, and a clip connected to the first power electrode. In this case, an integral part of the clip forms a shunt resistor and a first contact finger of the shunt resistor is embodied integrally with the clip.
    Type: Application
    Filed: April 30, 2019
    Publication date: November 14, 2019
    Inventors: Rainald Sander, Thomas Bemmerl, Steffen Thiele
  • Patent number: 10451669
    Abstract: Disclosed is a method, a circuit arrangement, and an electronic circuit. The method includes discharging a gate-source capacitance of a transistor device from a first voltage level to a second voltage level with a first resistor connected in parallel with the gate-source capacitance and measuring a first discharging time associated with the discharging, and discharging the gate-source capacitance from the first voltage level to the second voltage level with the first resistor and a second resistor connected in parallel with the gate-source capacitance and measuring a second discharging time associated with the discharging. The method further includes comparing a ratio between the first discharging time and the second discharging time with a predefined threshold, and detecting a fault based on the comparing.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: October 22, 2019
    Assignee: Infineon Technologies AG
    Inventors: Carlos Joao Marques Martins, Aron Theil, Steffen Thiele
  • Publication number: 20190101585
    Abstract: Disclosed is a method, a circuit arrangement, and an electronic circuit. The method includes discharging a gate-source capacitance of a transistor device from a first voltage level to a second voltage level with a first resistor connected in parallel with the gate-source capacitance and measuring a first discharging time associated with the discharging, and discharging the gate-source capacitance from the first voltage level to the second voltage level with the first resistor and a second resistor connected in parallel with the gate-source capacitance and measuring a second discharging time associated with the discharging. The method further includes comparing a ratio between the first discharging time and the second discharging time with a predefined threshold, and detecting a fault based on the comparing.
    Type: Application
    Filed: September 29, 2017
    Publication date: April 4, 2019
    Inventors: Carlos Joao Marques Martins, Aron Theil, Steffen Thiele
  • Patent number: 10128750
    Abstract: A switched-mode power converter includes an inductive storage element and a cascode circuit. The cascode circuit includes a double-gate field effect transistor. A switchable load path of the double-gate field effect transistor is electrically connected in series with the inductive storage element.
    Type: Grant
    Filed: March 4, 2016
    Date of Patent: November 13, 2018
    Assignee: Infineon Technologies AG
    Inventors: Andreas Meiser, Steffen Thiele
  • Patent number: 9960156
    Abstract: An integrated semiconductor device is provided. According to an embodiment, the integrated semiconductor device includes a semiconductor body having a first surface with a normal direction defining a vertical direction, an opposite surface, a first area including a vertical power field-effect transistor structure, a second area including a three-terminal step-down level-shifter, and a third area including a three-terminal step-up level-shifter. A terminal of the vertical power field-effect transistor structure is electrically connected with one of the three-terminal step-down level-shifter and the three-terminal step-up level-shifter.
    Type: Grant
    Filed: July 9, 2015
    Date of Patent: May 1, 2018
    Assignee: Infineon Technologies AG
    Inventors: Franz Hirler, Andreas Meiser, Steffen Thiele
  • Patent number: 9829225
    Abstract: The invention relates to a module for a heat pump, comprising an adsorption-desorption region, wherein in the region a bundle of pipes through which fluid can flow is arranged and a housing encloses the pipe bundle and a movable working medium in a sealing manner, wherein a supporting structure forms a mechanical support of a wall of the housing against the action of an external pressure.
    Type: Grant
    Filed: July 19, 2012
    Date of Patent: November 28, 2017
    Assignees: MAHLE Behr GmbH & Co. KG, MAHLE International GmbH
    Inventors: Thomas Schiehlen, Steffen Thiele, Thomas Wolff, Eberhard Zwittig, Hans-Heinrich Angermann, Roland Burk, Holger Schroth, Stefan Felber, Steffen Brunner
  • Publication number: 20170257025
    Abstract: A switched-mode power converter includes an inductive storage element and a cascode circuit. The cascode circuit includes a double-gate field effect transistor. A switchable load path of the double-gate field effect transistor is electrically connected in series with the inductive storage element.
    Type: Application
    Filed: March 4, 2016
    Publication date: September 7, 2017
    Inventors: Andreas Meiser, Steffen Thiele
  • Patent number: 9728580
    Abstract: A power transistor has a semiconductor body with a bottom side and top side spaced distant from the bottom side in a vertical direction. The semiconductor body includes a plurality of transistor cells, a source zone of a first conduction type, a body zone of a second conduction type, a drift zone of the first conduction type, a drain zone, and a temperature sensor diode having a pn-junction between an n-doped cathode zone and a p-doped anode zone. The power transistor also has a drain contact terminal on the top side, a source contact terminal on the bottom side, a gate contact terminal, and a temperature sense contact terminal on the top side. Depending on the first and second conduction types the anode or cathode zone is electrically connected to the source contact terminal and the other diode zone is electrically connected to the temperature sense contact terminal.
    Type: Grant
    Filed: May 13, 2013
    Date of Patent: August 8, 2017
    Assignee: Infineon Technologies AG
    Inventors: Andreas Meiser, Steffen Thiele
  • Publication number: 20170037150
    Abstract: The invention relates to the discovery and characterization of mannan binding lectin-associated serine protease-2 (MASP-2), a new serine protease that acts in the MBLectin complement fixation pathway.
    Type: Application
    Filed: August 3, 2016
    Publication date: February 9, 2017
    Inventors: Jens Chr. Jensenius, Steffen Thiel
  • Patent number: 9488674
    Abstract: A testing device in accordance with various embodiments may include: a plurality of first terminals configured to be connected to a plurality of devices-under-test, wherein each first terminal of the plurality of first terminals may be configured to be connected to a respective device-under-test of the plurality of devices-under-test; a signal interface configured to be connected to a tester; and a circuit configured to exchange an identical first signal with each device-under-test of the plurality of devices-under-test through a respective first terminal of the plurality of first terminals, and to exchange at least one interface signal with the tester through the signal interface.
    Type: Grant
    Filed: July 9, 2014
    Date of Patent: November 8, 2016
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Carlos Marques Martins, Steffen Thiele, Aron Theil
  • Patent number: 9441262
    Abstract: The invention relates to the discovery and characterization of mannan binding lectin-associated serine protease-2 (MASP-2), a new serine protease that acts in the MBLectin complement fixation pathway.
    Type: Grant
    Filed: September 19, 2013
    Date of Patent: September 13, 2016
    Assignee: Helion Biotech ApS
    Inventors: Jens Chr. Jensenius, Steffen Thiel