Patents by Inventor Stephan Borel

Stephan Borel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7910917
    Abstract: A microelectronic device provided with one or more quantum wires, able to form one or more transistor channels, and optimized in terms of arrangement, shape, and/or composition. A method for fabricating the device includes forming, in one or more thin layers resting on a support, a first block and a second block in which at least one transistor drain region and at least one transistor source region are respectively intended to be formed, forming a structure connecting the first block to the second block, and forming, on the surface of the structure, wires connecting a first region of the first block with another region of the second block that faces the first region.
    Type: Grant
    Filed: April 10, 2006
    Date of Patent: March 22, 2011
    Assignee: Commissariat a l'Energie Atomique
    Inventors: Thomas Ernst, Stephan Borel
  • Patent number: 7902575
    Abstract: The invention relates to a field-effect microelectronic device, as well as the method of production thereof. The device includes a substrate as well as at least one improved structure capable of forming one or more transistor channels. This structure, formed by a plurality of bars stacked on the substrate, can make it possible to save space in the integration of field-effect transistors as well as to improve the performance thereof.
    Type: Grant
    Filed: February 27, 2009
    Date of Patent: March 8, 2011
    Assignee: Commissariat a l'Energie Atomique
    Inventors: Thomas Ernst, Stephan Borel
  • Publication number: 20090194826
    Abstract: The invention relates to a field-effect microelectronic device, as well as the method of production thereof. The device includes a substrate as well as at least one improved structure capable of forming one or more transistor channels. This structure, formed by a plurality of bars stacked on the substrate, can make it possible to save space in the integration of field-effect transistors as well as to improve the performance thereof.
    Type: Application
    Filed: February 27, 2009
    Publication date: August 6, 2009
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE
    Inventors: Thomas ERNST, Stephan Borel
  • Publication number: 20090124088
    Abstract: A method of etching a sacrificial layer for a micro-machined structure, the sacrificial layer positioned between a layer of a first material and a layer of a second material, the etching being carried out by an etching agent. The method includes: providing at least one species having an affinity for the etching agent greater than that of the layers of first material and second material and less than or equal to that of the sacrificial layer; and then etching the sacrificial layer by the etching agent, the etching being carried out to eliminate at least partially the sacrificial layer and then to eliminate at least partially the species.
    Type: Application
    Filed: October 25, 2006
    Publication date: May 14, 2009
    Applicant: Copmissariat A L'Energie Atomique
    Inventors: Stephan Borel, Jeremy Bilde
  • Patent number: 7518195
    Abstract: The invention relates to a field-effect microelectronic device, and the production method thereof. Said device comprises a substrate (700) and at least one improved structure (702), capable of forming one or several transistor channels. Said structure, composed of several bars stacked on the substrate, may allow space saving in the integration of field-effect transistors and the performances thereof to be improved.
    Type: Grant
    Filed: October 21, 2004
    Date of Patent: April 14, 2009
    Assignee: Commissariat a l'Energie Atomique
    Inventors: Thomas Ernst, Stephan Borel
  • Patent number: 7436005
    Abstract: The insulated-gate field-effect transistor includes a substrate surmounted by a layer of silicon-germanium alloy, the ratio of the germanium concentration to the silicon concentration of which increases towards the surface of the substrate. The transistor is formed on the active zone in the silicon-germanium alloy layer and lies between two isolating zones. The transistor includes a narrow heterostructure strained-semiconductor channel including a SiGe alloy layer in compression and a silicon layer in tension, extending between the gate and a dielectric block buried in the substrate.
    Type: Grant
    Filed: September 15, 2005
    Date of Patent: October 14, 2008
    Assignees: STMicroelectronics (Crolles 2) SAS, Commissariat a l'Energie Atomique
    Inventors: Stéphane Monfray, Stéphan Borel, Thomas Skotnicki
  • Publication number: 20080149919
    Abstract: A microelectronic device provided with one or more quantum wires, able to form one or more transistor channels, and optimized in terms of arrangement, shape, and/or composition. A method for fabricating the device includes forming, in one or more thin layers resting on a support, a first block and a second block in which at least one transistor drain region and at least one transistor source region are respectively intended to be formed, forming a structure connecting the first block to the second block, and forming, on the surface of the structure, wires connecting a first region of the first block with another region of the second block that faces the first region.
    Type: Application
    Filed: April 10, 2006
    Publication date: June 26, 2008
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE
    Inventors: Thomas Ernst, Stephan Borel
  • Publication number: 20070126035
    Abstract: The invention relates to a field-effect microelectronic device, as well as the method of production thereof. The device includes a substrate (700) as well as at least one improved structure (702) capable of forming one or more transistor channels. This structure, formed by a plurality of bars stacked on the substrate, can make it possible to save space in the integration of field-effect transistors as well as to improve the performance thereof.
    Type: Application
    Filed: October 21, 2004
    Publication date: June 7, 2007
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE
    Inventors: Thomas Ernst, Stephan Borel
  • Publication number: 20060081876
    Abstract: The insulated-gate field-effect transistor includes a substrate surmounted by a layer of silicon-germanium alloy, the ratio of the germanium concentration to the silicon concentration of which increases towards the surface of the substrate. The transistor is formed on the active zone in the silicon-germanium alloy layer and lies between two isolating zones. The transistor includes a narrow heterostructure strained-semiconductor channel including a SiGe alloy layer in compression and a silicon layer in tension, extending between the gate and a dielectric block buried in the substrate.
    Type: Application
    Filed: September 15, 2005
    Publication date: April 20, 2006
    Applicants: STMicroelectronics (Crolles 2) SAS, Commissariat A L'Energie Atomique
    Inventors: Stephane Monfray, Stephan Borel, Thomas Skotnicki