Patents by Inventor Stephan Bradl
Stephan Bradl has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11652084Abstract: A method of forming a semiconductor package includes providing a panel, providing one or more metal layers on an upper surface of the panel, forming a die pad and bond pads from the one or more metal layers, the die pad being adjacent to and spaced apart from the bond pads, attaching a die to the die pad, forming electrical connections between the die and the bond pads, encapsulating the die and the electrical connections with an electrically insulating mold compound, removing portions of the panel, and exposing the die pad and the bond pads after encapsulating the die.Type: GrantFiled: October 23, 2020Date of Patent: May 16, 2023Assignee: Infineon Technologies AGInventors: Thorsten Meyer, Gerald Ofner, Stephan Bradl, Stefan Miethaner, Alexander Heinrich, Horst Theuss, Peter Scherl
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Patent number: 11410906Abstract: A semiconductor package for double sided cooling includes a first and a second carrier facing each other, at least one power semiconductor chip arranged between the first and second carriers, external contacts arranged at least partially between the first and second carriers, and spring elements arranged between the first and second carriers and configured to keep the first and second carriers at a predefined distance from each other.Type: GrantFiled: June 10, 2020Date of Patent: August 9, 2022Assignee: Infineon Technologies AGInventors: Juergen Hoegerl, Bernd Betz, Stephan Bradl, Daniel Obermeier
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Patent number: 11302668Abstract: A method of producing packaged semiconductor devices includes providing a first packaging substrate panel, providing a second packaging substrate panel, and moving the first and second packaging substrate panels through an assembly line that comprises a plurality of package assembly tools using a control mechanism. First type packaged semiconductor devices are formed on the first packaging substrate panel and second type packaged semiconductor devices are formed on the second packaging substrate panel. The control mechanism moves both of the first and packaging substrate panels through the assembly line in a non-linear manner. The first and second packaged semiconductor devices differ with respect to at least one of: lead configuration, and encapsulant configuration.Type: GrantFiled: December 19, 2019Date of Patent: April 12, 2022Assignee: Infineon Technologies AGInventors: Thorsten Meyer, Gerald Ofner, Stephan Bradl, Stefan Miethaner, Alexander Heinrich, Horst Theuss, Peter Scherl
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Publication number: 20210043603Abstract: A method of forming a semiconductor package includes providing a panel, providing one or more metal layers on an upper surface of the panel, forming a die pad and bond pads from the one or more metal layers, the die pad being adjacent to and spaced apart from the bond pads, attaching a die to the die pad, forming electrical connections between the die and the bond pads, encapsulating the die and the electrical connections with an electrically insulating mold compound, removing portions of the panel, and exposing the die pad and the bond pads after encapsulating the die.Type: ApplicationFiled: October 23, 2020Publication date: February 11, 2021Inventors: Thorsten Meyer, Gerald Ofner, Stephan Bradl, Stefan Miethaner, Alexander Heinrich, Horst Theuss, Peter Scherl
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Publication number: 20200395266Abstract: A semiconductor package for double sided cooling includes a first and a second carrier facing each other, at least one power semiconductor chip arranged between the first and second carriers, external contacts arranged at least partially between the first and second carriers, and spring elements arranged between the first and second carriers and configured to keep the first and second carriers at a predefined distance from each other.Type: ApplicationFiled: June 10, 2020Publication date: December 17, 2020Inventors: Juergen Hoegerl, Bernd Betz, Stephan Bradl, Daniel Obermeier
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Publication number: 20200203310Abstract: A method of producing packaged semiconductor devices includes providing a first packaging substrate panel, providing a second packaging substrate panel, and moving the first and second packaging substrate panels through an assembly line that comprises a plurality of package assembly tools using a control mechanism. First type packaged semiconductor devices are formed on the first packaging substrate panel and second type packaged semiconductor devices are formed on the second packaging substrate panel. The control mechanism moves both of the first and packaging substrate panels through the assembly line in a non-linear manner. The first and second packaged semiconductor devices differ with respect to at least one of: lead configuration, and encapsulant configuration.Type: ApplicationFiled: December 19, 2019Publication date: June 25, 2020Inventors: Thorsten Meyer, Gerald Ofner, Stephan Bradl, Stefan Miethaner, Alexander Heinrich, Horst Theuss, Peter Scherl
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Patent number: 10566309Abstract: A method of producing packaged semiconductor devices includes providing a first packaging substrate panel. A second packaging substrate panel is provided. The first and second packaging substrate panels are moved through an assembly line that includes a plurality of package assembly tools using a control mechanism. First type packaged semiconductor devices are formed on the first packaging substrate panel and second type packaged semiconductor devices are formed on the second packaging substrate panel. The second type packaged semiconductor device is different than the first type packaged semiconductor device. The control mechanism moves both of the first and packaging substrate panels through the assembly line in a non-linear manner.Type: GrantFiled: October 4, 2016Date of Patent: February 18, 2020Assignee: Infineon Technologies AGInventors: Thorsten Meyer, Gerald Ofner, Peter Scherl, Stephan Bradl, Stefan Miethaner, Alexander Heinrich, Horst Theuss
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Publication number: 20180096966Abstract: A method of producing packaged semiconductor devices includes providing a first packaging substrate panel. A second packaging substrate panel is provided. The first and second packaging substrate panels are moved through an assembly line that includes a plurality of package assembly tools using a control mechanism. First type packaged semiconductor devices are formed on the first packaging substrate panel and second type packaged semiconductor devices are formed on the second packaging substrate panel. The second type packaged semiconductor device is different than the first type packaged semiconductor device. The control mechanism moves both of the first and packaging substrate panels through the assembly line in a non-linear manner.Type: ApplicationFiled: October 4, 2016Publication date: April 5, 2018Inventors: Thorsten Meyer, Gerald Ofner, Peter Scherl, Stephan Bradl, Stefan Miethaner, Alexander Heinrich, Horst Theuss
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Patent number: 9601475Abstract: A workpiece has at least two semiconductor chips, each semiconductor chip having a first main surface, which is at least partially exposed, and a second main surface. The workpiece also comprises an electrically conducting layer, arranged on the at least two semiconductor chips, the electrically conducting layer being arranged at least on regions of the second main surface, and a molding compound, arranged on the electrically conducting layer.Type: GrantFiled: February 11, 2016Date of Patent: March 21, 2017Assignee: Intel Deutschland GmbHInventors: Markus Brunnbauer, Thorsten Meyer, Stephan Bradl, Ralf Plieninger, Jens Pohl, Klaus Pressel, Recai Sezi
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Publication number: 20160163682Abstract: A workpiece has at least two semiconductor chips, each semiconductor chip having a first main surface, which is at least partially exposed, and a second main surface. The workpiece also comprises an electrically conducting layer, arranged on the at least two semiconductor chips, the electrically conducting layer being arranged at least on regions of the second main surface, and a molding compound, arranged on the electrically conducting layer.Type: ApplicationFiled: February 11, 2016Publication date: June 9, 2016Inventors: Markus Brunnbauer, Thorsten Meyer, Stephan Bradl, Ralf Plieninger, Jens Pohl, Klaus Pressel, Recai Sezi
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Patent number: 9293423Abstract: A workpiece has at least two semiconductor chips, each semiconductor chip having a first main surface, which is at least partially exposed, and a second main surface. The workpiece also comprises an electrically conducting layer, arranged on the at least two semiconductor chips, the electrically conducting layer being arranged at least on regions of the second main surface, and a molding compound, arranged on the electrically conducting layer.Type: GrantFiled: July 14, 2014Date of Patent: March 22, 2016Assignee: Intel Deutschland GmbHInventors: Markus Brunnbauer, Thorsten Meyer, Stephan Bradl, Ralf Plieninger, Jens Pohl, Klaus Pressel, Recai Sezi
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Publication number: 20140332937Abstract: A workpiece has at least two semiconductor chips, each semiconductor chip having a first main surface, which is at least partially exposed, and a second main surface. The workpiece also comprises an electrically conducting layer, arranged on the at least two semiconductor chips, the electrically conducting layer being arranged at least on regions of the second main surface, and a molding compound, arranged on the electrically conducting layer.Type: ApplicationFiled: July 14, 2014Publication date: November 13, 2014Inventors: Markus Brunnbauer, Thorsten Meyer, Stephan Bradl, Ralf Plieninger, Jens Pohl, Klaus Pressel, Recai Sezi
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Patent number: 8759230Abstract: The invention relates to an arrangement of electronic semiconductor components on a carrier system for treating the semiconductor components with a liquid medium. A semiconductor component is detachably mounted on the carrier system with the active side thereof in such a way that the arrangement comprises a gap at least in the edge region and partially between the semiconductor components and the carrier system. The aim of the invention is to provide a detachable arrangement of electronic semiconductor components on a mechanically stable carrier system for safely handling the semiconductor components during the production process, wherein the capillarity of the gap between the semiconductor components and the carrier system is reduced in a controlled manner, thus preventing the damaging effect of a liquid medium seeping into the gap. To this end, the surface of the carrier system is shaped in such a way that the gap is widened along the entire edge region thereof.Type: GrantFiled: December 9, 2008Date of Patent: June 24, 2014Assignee: Infineon Technologies AGInventors: Stephan Bradl, Michael Melzl, Josef Schwaiger, Thilo Stache
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Patent number: 8309454Abstract: A workpiece has at least two semiconductor chips, each semiconductor chip having a first main surface, which is at least partially exposed, and a second main surface. The workpiece also comprises an electrically conducting layer, arranged on the at least two semiconductor chips, the electrically conducting layer being arranged at least on regions of the second main surface, and a molding compound, arranged on the electrically conducting layer.Type: GrantFiled: May 10, 2007Date of Patent: November 13, 2012Assignee: Intel Mobile Communications GmbHInventors: Markus Brunnbauer, Thorsten Meyer, Stephan Bradl, Ralf Plieninger, Jens Pohl, Klaus Pressel, Recai Sezi
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Patent number: 8173534Abstract: A semiconductor wafer with rear side identification and to a method for producing the same is disclosed. In one embodiment, the rear side identification has a multiplicity of information regarding the monocrystalline and surface and also rear side constitution. A multiplicity of semiconductor device positions arranged in rows and columns are provided on the top side of the semiconductor wafer, an information chip being arranged at an exposed semiconductor device position, the information chip having at least the information of the rear side identification.Type: GrantFiled: February 28, 2011Date of Patent: May 8, 2012Assignee: Infineon Technologies AGInventors: Stephan Bradl, Rainer Holmer
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Publication number: 20120058362Abstract: Various embodiments provide a method for depositing metal on a substrate. The method may include carrying out a first immersion plating process, thereby forming a first metal portion on the substrate; providing an immersion plating activating substance on the first metal portion; and carrying out a second immersion plating process using the immersion plating activating substance, thereby forming a second metal portion on the first metal portion.Type: ApplicationFiled: September 8, 2010Publication date: March 8, 2012Applicant: INFINEON TECHNOLOGIES AGInventors: Markus Zistler, Stephan Bradl
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Publication number: 20110147471Abstract: A semiconductor wafer with rear side identification and to a method for producing the same is disclosed. In one embodiment, the rear side identification has a multiplicity of information regarding the monocrystalline and surface and also rear side constitution. A multiplicity of semiconductor device positions arranged in rows and columns are provided on the top side of the semiconductor wafer, an information chip being arranged at an exposed semiconductor device position, the information chip having at least the information of the rear side identification.Type: ApplicationFiled: February 28, 2011Publication date: June 23, 2011Applicant: INFINEON TECHNOLOGIES AGInventors: Stephan Bradl, Rainer Holmer
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Publication number: 20110115096Abstract: A method is described in which a contact hole to an interconnect in an insulating layer is fabricated. A barrier layer is subsequently applied. Afterward, a photoresist layer is applied, irradiated and developed. With the aid of a galvanic method, a copper contact is then produced in the contact hole. Either the barrier layer or an additional boundary electrode layer serves as a boundary electrode in the galvanic process. Critical metal contaminations are minimized in production.Type: ApplicationFiled: January 25, 2011Publication date: May 19, 2011Applicant: Infineon Technologies AGInventors: Stephan Bradl, Klaus Kerkel, Christine Lindner
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Patent number: 7911036Abstract: A semiconductor wafer with rear side identification and to a method for producing the same is disclosed. In one embodiment, the rear side identification has a multiplicity of information regarding the monocrystalline and surface and also rear side constitution. A multiplicity of semiconductor device positions arranged in rows and columns are provided on the top side of the semiconductor wafer, an information chip being arranged at an exposed semiconductor device position, the information chip having at least the information of the rear side identification.Type: GrantFiled: January 11, 2007Date of Patent: March 22, 2011Assignee: Infineon Technologies AGInventors: Stephan Bradl, Rainer Holmer
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Patent number: 7906860Abstract: A semiconductor device is disclosed. One embodiment provides an arrangement of a plurality of semiconductor chips arranged side by side in a spaced apart relationship. A first material fills at least partly the spacings between adjacent semiconductor chips. A second material is arranged over the semiconductor chips and the first material. A coefficient of thermal expansion of the first material is selected to adapt the lateral thermal expansion of the arrangement in a plane intersecting the first material and the semiconductor chips to the lateral thermal expansion of the arrangement in a plane intersecting the second material.Type: GrantFiled: October 26, 2007Date of Patent: March 15, 2011Assignee: Infineon Technologies AGInventors: Thorsten Meyer, Markus Brunnbauer, Marcus Kastner, Stephan Bradl