Patents by Inventor Stephan Bradl

Stephan Bradl has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210043603
    Abstract: A method of forming a semiconductor package includes providing a panel, providing one or more metal layers on an upper surface of the panel, forming a die pad and bond pads from the one or more metal layers, the die pad being adjacent to and spaced apart from the bond pads, attaching a die to the die pad, forming electrical connections between the die and the bond pads, encapsulating the die and the electrical connections with an electrically insulating mold compound, removing portions of the panel, and exposing the die pad and the bond pads after encapsulating the die.
    Type: Application
    Filed: October 23, 2020
    Publication date: February 11, 2021
    Inventors: Thorsten Meyer, Gerald Ofner, Stephan Bradl, Stefan Miethaner, Alexander Heinrich, Horst Theuss, Peter Scherl
  • Publication number: 20200395266
    Abstract: A semiconductor package for double sided cooling includes a first and a second carrier facing each other, at least one power semiconductor chip arranged between the first and second carriers, external contacts arranged at least partially between the first and second carriers, and spring elements arranged between the first and second carriers and configured to keep the first and second carriers at a predefined distance from each other.
    Type: Application
    Filed: June 10, 2020
    Publication date: December 17, 2020
    Inventors: Juergen Hoegerl, Bernd Betz, Stephan Bradl, Daniel Obermeier
  • Publication number: 20200203310
    Abstract: A method of producing packaged semiconductor devices includes providing a first packaging substrate panel, providing a second packaging substrate panel, and moving the first and second packaging substrate panels through an assembly line that comprises a plurality of package assembly tools using a control mechanism. First type packaged semiconductor devices are formed on the first packaging substrate panel and second type packaged semiconductor devices are formed on the second packaging substrate panel. The control mechanism moves both of the first and packaging substrate panels through the assembly line in a non-linear manner. The first and second packaged semiconductor devices differ with respect to at least one of: lead configuration, and encapsulant configuration.
    Type: Application
    Filed: December 19, 2019
    Publication date: June 25, 2020
    Inventors: Thorsten Meyer, Gerald Ofner, Stephan Bradl, Stefan Miethaner, Alexander Heinrich, Horst Theuss, Peter Scherl
  • Patent number: 10566309
    Abstract: A method of producing packaged semiconductor devices includes providing a first packaging substrate panel. A second packaging substrate panel is provided. The first and second packaging substrate panels are moved through an assembly line that includes a plurality of package assembly tools using a control mechanism. First type packaged semiconductor devices are formed on the first packaging substrate panel and second type packaged semiconductor devices are formed on the second packaging substrate panel. The second type packaged semiconductor device is different than the first type packaged semiconductor device. The control mechanism moves both of the first and packaging substrate panels through the assembly line in a non-linear manner.
    Type: Grant
    Filed: October 4, 2016
    Date of Patent: February 18, 2020
    Assignee: Infineon Technologies AG
    Inventors: Thorsten Meyer, Gerald Ofner, Peter Scherl, Stephan Bradl, Stefan Miethaner, Alexander Heinrich, Horst Theuss
  • Publication number: 20180096966
    Abstract: A method of producing packaged semiconductor devices includes providing a first packaging substrate panel. A second packaging substrate panel is provided. The first and second packaging substrate panels are moved through an assembly line that includes a plurality of package assembly tools using a control mechanism. First type packaged semiconductor devices are formed on the first packaging substrate panel and second type packaged semiconductor devices are formed on the second packaging substrate panel. The second type packaged semiconductor device is different than the first type packaged semiconductor device. The control mechanism moves both of the first and packaging substrate panels through the assembly line in a non-linear manner.
    Type: Application
    Filed: October 4, 2016
    Publication date: April 5, 2018
    Inventors: Thorsten Meyer, Gerald Ofner, Peter Scherl, Stephan Bradl, Stefan Miethaner, Alexander Heinrich, Horst Theuss
  • Patent number: 9601475
    Abstract: A workpiece has at least two semiconductor chips, each semiconductor chip having a first main surface, which is at least partially exposed, and a second main surface. The workpiece also comprises an electrically conducting layer, arranged on the at least two semiconductor chips, the electrically conducting layer being arranged at least on regions of the second main surface, and a molding compound, arranged on the electrically conducting layer.
    Type: Grant
    Filed: February 11, 2016
    Date of Patent: March 21, 2017
    Assignee: Intel Deutschland GmbH
    Inventors: Markus Brunnbauer, Thorsten Meyer, Stephan Bradl, Ralf Plieninger, Jens Pohl, Klaus Pressel, Recai Sezi
  • Publication number: 20160163682
    Abstract: A workpiece has at least two semiconductor chips, each semiconductor chip having a first main surface, which is at least partially exposed, and a second main surface. The workpiece also comprises an electrically conducting layer, arranged on the at least two semiconductor chips, the electrically conducting layer being arranged at least on regions of the second main surface, and a molding compound, arranged on the electrically conducting layer.
    Type: Application
    Filed: February 11, 2016
    Publication date: June 9, 2016
    Inventors: Markus Brunnbauer, Thorsten Meyer, Stephan Bradl, Ralf Plieninger, Jens Pohl, Klaus Pressel, Recai Sezi
  • Patent number: 9293423
    Abstract: A workpiece has at least two semiconductor chips, each semiconductor chip having a first main surface, which is at least partially exposed, and a second main surface. The workpiece also comprises an electrically conducting layer, arranged on the at least two semiconductor chips, the electrically conducting layer being arranged at least on regions of the second main surface, and a molding compound, arranged on the electrically conducting layer.
    Type: Grant
    Filed: July 14, 2014
    Date of Patent: March 22, 2016
    Assignee: Intel Deutschland GmbH
    Inventors: Markus Brunnbauer, Thorsten Meyer, Stephan Bradl, Ralf Plieninger, Jens Pohl, Klaus Pressel, Recai Sezi
  • Publication number: 20140332937
    Abstract: A workpiece has at least two semiconductor chips, each semiconductor chip having a first main surface, which is at least partially exposed, and a second main surface. The workpiece also comprises an electrically conducting layer, arranged on the at least two semiconductor chips, the electrically conducting layer being arranged at least on regions of the second main surface, and a molding compound, arranged on the electrically conducting layer.
    Type: Application
    Filed: July 14, 2014
    Publication date: November 13, 2014
    Inventors: Markus Brunnbauer, Thorsten Meyer, Stephan Bradl, Ralf Plieninger, Jens Pohl, Klaus Pressel, Recai Sezi
  • Patent number: 8759230
    Abstract: The invention relates to an arrangement of electronic semiconductor components on a carrier system for treating the semiconductor components with a liquid medium. A semiconductor component is detachably mounted on the carrier system with the active side thereof in such a way that the arrangement comprises a gap at least in the edge region and partially between the semiconductor components and the carrier system. The aim of the invention is to provide a detachable arrangement of electronic semiconductor components on a mechanically stable carrier system for safely handling the semiconductor components during the production process, wherein the capillarity of the gap between the semiconductor components and the carrier system is reduced in a controlled manner, thus preventing the damaging effect of a liquid medium seeping into the gap. To this end, the surface of the carrier system is shaped in such a way that the gap is widened along the entire edge region thereof.
    Type: Grant
    Filed: December 9, 2008
    Date of Patent: June 24, 2014
    Assignee: Infineon Technologies AG
    Inventors: Stephan Bradl, Michael Melzl, Josef Schwaiger, Thilo Stache
  • Patent number: 8309454
    Abstract: A workpiece has at least two semiconductor chips, each semiconductor chip having a first main surface, which is at least partially exposed, and a second main surface. The workpiece also comprises an electrically conducting layer, arranged on the at least two semiconductor chips, the electrically conducting layer being arranged at least on regions of the second main surface, and a molding compound, arranged on the electrically conducting layer.
    Type: Grant
    Filed: May 10, 2007
    Date of Patent: November 13, 2012
    Assignee: Intel Mobile Communications GmbH
    Inventors: Markus Brunnbauer, Thorsten Meyer, Stephan Bradl, Ralf Plieninger, Jens Pohl, Klaus Pressel, Recai Sezi
  • Patent number: 8173534
    Abstract: A semiconductor wafer with rear side identification and to a method for producing the same is disclosed. In one embodiment, the rear side identification has a multiplicity of information regarding the monocrystalline and surface and also rear side constitution. A multiplicity of semiconductor device positions arranged in rows and columns are provided on the top side of the semiconductor wafer, an information chip being arranged at an exposed semiconductor device position, the information chip having at least the information of the rear side identification.
    Type: Grant
    Filed: February 28, 2011
    Date of Patent: May 8, 2012
    Assignee: Infineon Technologies AG
    Inventors: Stephan Bradl, Rainer Holmer
  • Publication number: 20120058362
    Abstract: Various embodiments provide a method for depositing metal on a substrate. The method may include carrying out a first immersion plating process, thereby forming a first metal portion on the substrate; providing an immersion plating activating substance on the first metal portion; and carrying out a second immersion plating process using the immersion plating activating substance, thereby forming a second metal portion on the first metal portion.
    Type: Application
    Filed: September 8, 2010
    Publication date: March 8, 2012
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Markus Zistler, Stephan Bradl
  • Publication number: 20110147471
    Abstract: A semiconductor wafer with rear side identification and to a method for producing the same is disclosed. In one embodiment, the rear side identification has a multiplicity of information regarding the monocrystalline and surface and also rear side constitution. A multiplicity of semiconductor device positions arranged in rows and columns are provided on the top side of the semiconductor wafer, an information chip being arranged at an exposed semiconductor device position, the information chip having at least the information of the rear side identification.
    Type: Application
    Filed: February 28, 2011
    Publication date: June 23, 2011
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Stephan Bradl, Rainer Holmer
  • Publication number: 20110115096
    Abstract: A method is described in which a contact hole to an interconnect in an insulating layer is fabricated. A barrier layer is subsequently applied. Afterward, a photoresist layer is applied, irradiated and developed. With the aid of a galvanic method, a copper contact is then produced in the contact hole. Either the barrier layer or an additional boundary electrode layer serves as a boundary electrode in the galvanic process. Critical metal contaminations are minimized in production.
    Type: Application
    Filed: January 25, 2011
    Publication date: May 19, 2011
    Applicant: Infineon Technologies AG
    Inventors: Stephan Bradl, Klaus Kerkel, Christine Lindner
  • Patent number: 7911036
    Abstract: A semiconductor wafer with rear side identification and to a method for producing the same is disclosed. In one embodiment, the rear side identification has a multiplicity of information regarding the monocrystalline and surface and also rear side constitution. A multiplicity of semiconductor device positions arranged in rows and columns are provided on the top side of the semiconductor wafer, an information chip being arranged at an exposed semiconductor device position, the information chip having at least the information of the rear side identification.
    Type: Grant
    Filed: January 11, 2007
    Date of Patent: March 22, 2011
    Assignee: Infineon Technologies AG
    Inventors: Stephan Bradl, Rainer Holmer
  • Patent number: 7906860
    Abstract: A semiconductor device is disclosed. One embodiment provides an arrangement of a plurality of semiconductor chips arranged side by side in a spaced apart relationship. A first material fills at least partly the spacings between adjacent semiconductor chips. A second material is arranged over the semiconductor chips and the first material. A coefficient of thermal expansion of the first material is selected to adapt the lateral thermal expansion of the arrangement in a plane intersecting the first material and the semiconductor chips to the lateral thermal expansion of the arrangement in a plane intersecting the second material.
    Type: Grant
    Filed: October 26, 2007
    Date of Patent: March 15, 2011
    Assignee: Infineon Technologies AG
    Inventors: Thorsten Meyer, Markus Brunnbauer, Marcus Kastner, Stephan Bradl
  • Patent number: 7902062
    Abstract: A method is described in which a contact hole (18) to an interconnect (14) in an insulating layer (16) is fabricated. A barrier layer (20) is subsequently applied. Afterward, a photoresist layer (30) is applied, irradiated and developed. With the aid of a galvanic method, a copper contact (32) is then produced in the contact hole (18). Either the barrier layer (20) or an additional boundary electrode layer (22) serves as a boundary electrode in the galvanic process. Critical metal contaminations are minimized in production.
    Type: Grant
    Filed: May 23, 2005
    Date of Patent: March 8, 2011
    Assignee: Infineon Technologies AG
    Inventors: Stephan Bradl, Klaus Kerkel, Christine Lindner
  • Patent number: 7759792
    Abstract: An integrated circuit includes a substrate including a contact pad, a redistribution line coupled to the contact pad, and a dielectric material layer between the substrate and the redistribution line. The integrated circuit includes a solder ball coupled to the redistribution line and a parylene material layer sealing the dielectric material layer and the redistribution line.
    Type: Grant
    Filed: August 15, 2007
    Date of Patent: July 20, 2010
    Assignee: Infineon Technologies AG
    Inventors: Thorsten Meyer, Markus Brunnbauer, Stephan Bradl
  • Patent number: 7687895
    Abstract: A workpiece has at least two semiconductor chips, each semiconductor chip having a first main surface, which is at least partially exposed, and a second main surface. The workpiece also includes an electrically conducting layer, arranged on the at least two semiconductor chips, the electrically conducting layer being arranged at least on regions of the second main surface, and a molding compound, arranged on the electrically conducting layer. In the molding compound a contact via is arranged.
    Type: Grant
    Filed: November 14, 2007
    Date of Patent: March 30, 2010
    Assignee: Infineon Technologies AG
    Inventors: Markus Brunnbauer, Jens Pohl, Klaus Pressel, Thorsten Meyer, Recai Sezi, Stephan Bradl, Ralf Plieninger