Patents by Inventor Stephan Leuschner

Stephan Leuschner has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11936293
    Abstract: A regulated charge pump includes a comparator having a first input coupled to an output of the regulated charge pump, a second input configured for receiving a reference voltage, and an output for generating an output voltage representing a difference between a charging current of the regulated charge pump and a load current of a load coupled to the output of the regulated charge pump; a first converter having an input coupled to the output of the comparator, and an output connected to a control bus configured to indicate an adjustment of the charging current in response to the comparator output; and a driving stage having a first input coupled to the control bus, and an output for providing the charging current, wherein the output of the driving stage comprises the output of the regulated charge pump.
    Type: Grant
    Filed: June 17, 2022
    Date of Patent: March 19, 2024
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Semen Syroiezhin, Andreas Baenisch, Stephan Leuschner, Andreas Wickmann
  • Publication number: 20230412071
    Abstract: A regulated charge pump includes a comparator having a first input coupled to an output of the regulated charge pump, a second input configured for receiving a reference voltage, and an output for generating an output voltage representing a difference between a charging current of the regulated charge pump and a load current of a load coupled to the output of the regulated charge pump; a first converter having an input coupled to the output of the comparator, and an output connected to a control bus configured to indicate an adjustment of the charging current in response to the comparator output; and a driving stage having a first input coupled to the control bus, and an output for providing the charging current, wherein the output of the driving stage comprises the output of the regulated charge pump.
    Type: Application
    Filed: June 17, 2022
    Publication date: December 21, 2023
    Inventors: Semen Syroiezhin, Andreas Baenisch, Stephan Leuschner, Andreas Wickmann
  • Publication number: 20230144365
    Abstract: A holding element positions back parts or parts thereof of poultry carcasses having a neck side, a hip side, a body exterior side, and a body interior side, wherein the back part has a spinal column or parts thereof and a rib structure having at least vertebral rib pairs or parts thereof. The back part has a region, on the exterior side of the body relative to the rib structure, that has back-flesh. The holding element includes a holding device with at least one controllable clamping element. The at least one clamping element is configured and adapted to releasably fix the back part at least in some regions on the holding device by non-positive and/or positive locking engagement with the body interior side.
    Type: Application
    Filed: March 24, 2021
    Publication date: May 11, 2023
    Inventors: Stephan Leuschner, Andreas Landt, Lasse Riggert
  • Patent number: 11632108
    Abstract: Techniques are provided for fanning out a signal from a balun. In various aspects, the system can include a balun configured to receive a signal for transmission at an input and to provide a representation of the signal at an output, a plurality of pass gate circuits, each pass gate circuit configured to receive the representation of the signal at a first node, to receive a control signal at a second node to pass the representation of the signal to a third node when the control signal is in a first state, and to isolate the representation of the signal from the third node when the control signal is in a second state. The first state of the control signal can include a non-zero voltage, and the second state of the control signal can include the non-zero voltage with a polarity opposite the non-zero voltage of the first state.
    Type: Grant
    Filed: February 11, 2022
    Date of Patent: April 18, 2023
    Assignee: Intel Corporation
    Inventors: Chuanzhao Yu, Stephan Leuschner, David Newman
  • Publication number: 20230111076
    Abstract: An apparatus and method is for recovering back-flesh from back parts of poultry carcasses having a hip side and body interior side. The back part includes a spinal column and rib structure. A transport conveyor transports the back parts along a transport path with a centre axis in a direction of transport and has a transport element for conveying at least one holding element, arranged on the transport element, for receiving the back part. A first cutting assembly is along the transport path in the region of the transport element and has a loosening means for loosening the back-flesh along the rib structure. A second cutting assembly is along the transport path downstream of the first assembly and has at least one separating knife for separating the back-flesh substantially along the spinal column. The holding element holds the back part on the holding element by non-positive and/or positive locking engagement.
    Type: Application
    Filed: March 24, 2021
    Publication date: April 13, 2023
    Inventors: Stephan Leuschner, Andreas Landt, Lasse Riggert
  • Patent number: 11575036
    Abstract: Gallium nitride (GaN) transistors with source and drain field plates are described. In an example, a transistor includes a gallium nitride (GaN) layer above a substrate, a gate structure over the GaN layer, a source region on a first side of the gate structure, a drain region on a second side of the gate structure, the second side opposite the first side, a source field plate above the source region, and a drain field plate above the drain region.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: February 7, 2023
    Assignee: Intel Corporation
    Inventors: Han Wui Then, Stephan Leuschner, Marko Radosavljevic, Sansaptak Dasgupta
  • Patent number: 11545586
    Abstract: A Group III-Nitride (III-N) device structure is provided which comprises: a heterostructure having three or more layers comprising III-N material, an anode within a recess that extends through two or more of the layers, wherein the anode is in electrical contact with the first layer, a cathode comprising donor dopants, wherein the cathode is on the first layer of the heterostructure; and a conducting region in the first layer in direct contact to the cathode and conductively connected to the anode. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: January 3, 2023
    Assignee: Intel Corporation
    Inventors: Harald Gossner, Peter Baumgartner, Uwe Hodel, Domagoj Siprak, Stephan Leuschner, Richard Geiger, Han Wui Then, Marko Radosavljevic, Sansaptak Dasgupta
  • Patent number: 11528041
    Abstract: A method of manufacturing an RF switch includes adding a first mutual inductance portion to a first self-inductance portion of a first transmission line; and adding a second mutual inductance portion to a second self-inductance portion of a second transmission line, wherein values of the first and second mutual inductance portions and values of the first and second self-inductance portions equalize an impedance difference between the first transmission line and the second transmission line.
    Type: Grant
    Filed: April 7, 2020
    Date of Patent: December 13, 2022
    Assignee: Infineon Technologies AG
    Inventors: Pierpaolo Verzola, Stephan Leuschner
  • Publication number: 20220320350
    Abstract: A variable capacitance III-N device having multiple two-dimensional electron gas (2DEG) layers are described. In some embodiments, the device comprises a first source and a first drain; a first polarization layer adjacent to the first source and the first drain; a first channel layer coupled to the first source and the first drain and adjacent to the first polarization layer, the first channel layer comprising a first 2DEG region; a second source and a second drain; a second polarization layer adjacent to the second source and the second drain; and a second channel layer coupled to the second source and the second drain and adjacent to the second polarization layer, the second channel layer comprising a second 2DEG region, wherein the second channel layer is over the first polarization layer.
    Type: Application
    Filed: June 23, 2022
    Publication date: October 6, 2022
    Applicant: Intel Corporation
    Inventors: Harald Gossner, Peter Baumgartner, Uwe Hodel, Domagoj Siprak, Stephan Leuschner, Richard Geiger, Han Wui Then, Marko Radosavljevic, Sansaptak Dasgupta
  • Patent number: 11424354
    Abstract: A Group III-Nitride (III-N) device structure is provided comprising: a heterostructure having three or more layers comprising III-N material, an anode n+ region and a cathode comprising donor dopants, wherein the anode n+ region and the cathode are on the first layer of the heterostructure and wherein the anode n+ region and the cathode extend beyond the heterostructure, and an anode metal region within a recess that extends through two or more of the layers, wherein the anode metal region is in electrical contact with the first layer, wherein the anode metal region comprises a first width within the recess and a second width beyond the recess, and wherein the anode metal region is coupled with the anode n+ region. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: August 23, 2022
    Assignee: Intel Corporation
    Inventors: Harald Gossner, Peter Baumgartner, Uwe Hodel, Domagoj Siprak, Stephan Leuschner, Richard Geiger
  • Patent number: 11380806
    Abstract: A variable capacitance III-N device having multiple two-dimensional electron gas (2DEG) layers are described. In some embodiments, the device comprises a first source and a first drain; a first polarization layer adjacent to the first source and the first drain; a first channel layer coupled to the first source and the first drain and adjacent to the first polarization layer, the first channel layer comprising a first 2DEG region; a second source and a second drain; a second polarization layer adjacent to the second source and the second drain; and a second channel layer coupled to the second source and the second drain and adjacent to the second polarization layer, the second channel layer comprising a second 2DEG region, wherein the second channel layer is over the first polarization layer.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: July 5, 2022
    Assignee: Intel Corporation
    Inventors: Harald Gossner, Peter Baumgartner, Uwe Hodel, Domagoj Siprak, Stephan Leuschner, Richard Geiger, Han Wui Then, Marko Radosavljevic, Sansaptak Dasgupta
  • Patent number: 11373995
    Abstract: A Group III-Nitride (III-N) device structure is presented comprising: a heterostructure having three or more layers comprising III-N material, a cathode comprising donor dopants, wherein the cathode is on a first layer of the heterostructure, an anode within a recess that extends through two or more of the layers of the heterostructure, wherein the anode comprises a first region wherein the anode is separated from the heterostructure by a high k dielectric material, and a second region wherein the anode is in direct contact with the heterostructure, and a conducting region in the first layer in direct contact to the cathode and conductively connected to the anode. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: June 28, 2022
    Assignee: Intel Corporation
    Inventors: Harald Gossner, Peter Baumgartner, Uwe Hodel, Domagoj Siprak, Stephan Leuschner, Richard Geiger, Han Wui Then, Marko Radosavljevic, Sansaptak Dasgupta
  • Publication number: 20220166430
    Abstract: Techniques are provided for fanning out a signal from a balun. In various aspects, the system can include a balun configured to receive a signal for transmission at an input and to provide a representation of the signal at an output, a plurality of pass gate circuits, each pass gate circuit configured to receive the representation of the signal at a first node, to receive a control signal at a second node to pass the representation of the signal to a third node when the control signal is in a first state, and to isolate the representation of the signal from the third node when the control signal is in a second state. The first state of the control signal can include a non-zero voltage, and the second state of the control signal can include the non-zero voltage with a polarity opposite the non-zero voltage of the first state.
    Type: Application
    Filed: February 11, 2022
    Publication date: May 26, 2022
    Inventors: Chuanzhao Yu, Stephan Leuschner, David Newman
  • Patent number: 11283444
    Abstract: Techniques are provided for fanning out a signal from a balun. In various aspects, the system can include a balun configured to receive a signal for transmission at an input and to provide a representation of the signal at an output, a plurality of pass gate circuits, each pass gate circuit configured to receive the representation of the signal at a first node, to receive a control signal at a second node to pass the representation of the signal to a third node when the control signal is in a first state, and to isolate the representation of the signal from the third node when the control signal is in a second state. The first state of the control signal can include a non-zero voltage, and the second state of the control signal can include the non-zero voltage with a polarity opposite the non-zero voltage of the first state.
    Type: Grant
    Filed: March 28, 2018
    Date of Patent: March 22, 2022
    Assignee: Intel Corporation
    Inventors: Chuanzhao Yu, Stephan Leuschner, David Newman
  • Publication number: 20210314006
    Abstract: A method of manufacturing an RF switch includes adding a first mutual inductance portion to a first self-inductance portion of a first transmission line; and adding a second mutual inductance portion to a second self-inductance portion of a second transmission line, wherein values of the first and second mutual inductance portions and values of the first and second self-inductance portions equalize an impedance difference between the first transmission line and the second transmission line.
    Type: Application
    Filed: April 7, 2020
    Publication date: October 7, 2021
    Inventors: Pierpaolo Verzola, Stephan Leuschner
  • Patent number: 11050411
    Abstract: Examples provide a wideband filter structure and apparatus, a radio transceiver, a mobile terminal, and a method for filtering a radio signal. The wideband filter structure (10) for a radio signal comprises a combination of at least one acoustic resonator (12) and at least one analog resonator (14). The acoustic resonator (12) is coupled to the analog resonator (14). The wideband filter structure (10) comprises a further component (16), which is coupled to the combination of the acoustic resonator (12) and the analog resonator (14).
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: June 29, 2021
    Assignee: Intel IP Corporation
    Inventors: Michael Wagner, Stephan Leuschner
  • Publication number: 20200411699
    Abstract: A Group III-Nitride (III-N) device structure is provided which comprises: a heterostructure having three or more layers comprising III-N material, an anode within a recess that extends through two or more of the layers, wherein the anode is in electrical contact with the first layer, a cathode comprising donor dopants, wherein the cathode is on the first layer of the heterostructure; and a conducting region in the first layer in direct contact to the cathode and conductively connected to the anode. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: September 29, 2017
    Publication date: December 31, 2020
    Applicant: INTEL CORPORATION
    Inventors: Harald Gossner, Peter Baumgartner, Uwe Hodel, Domagoj Siprak, Stephan Leuschner, Richard Geiger, Han Wui Then, Marko Radosavljevic, Sansaptak Dasgupta
  • Publication number: 20200411505
    Abstract: A Group III-Nitride (III-N) device structure is presented comprising: a heterostructure having three or more layers comprising material, a cathode comprising donor dopants, wherein the cathode is on a first layer of the heterostructure, an anode within a recess that extends through two or more of the layers of the heterostructure, wherein the anode comprises a first region wherein the anode is separated from the heterostructure by a high k dielectric material, and a second region wherein the anode is in direct contact with the heterostructure, and a conducting region in the first layer in direct contact to the cathode and conductively connected to the anode. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: September 29, 2017
    Publication date: December 31, 2020
    Applicant: INTEL CORPORATION
    Inventors: Harald Gossner, Peter Baumgartner, Uwe Hodel, Domagoj Siprak, Stephan Leuschner, Richard Geiger, Han Wui Then, Marko Radosavljevic, Sansaptak Dasgupta
  • Publication number: 20200227544
    Abstract: Gallium nitride (GaN) transistors with drain field plates and their methods of fabrication are described. In an example, a transistor includes a gallium nitride (GaN) layer above a substrate, a gate structure over the GaN layer, a source region on a first side of the gate structure, a drain region on a second side of the gate structure, the second side opposite the first side, and a drain field plate above the drain region, wherein the drain field plate is not electrically coupled to the gate structure or the source region.
    Type: Application
    Filed: September 28, 2017
    Publication date: July 16, 2020
    Inventors: Han Wui THEN, Stephan LEUSCHNER, Marko RADOSAVLJEVIC, Sansaptak DASGUPTA
  • Publication number: 20200227545
    Abstract: Gallium nitride (GaN) transistors with source and drain field plates are described. In an example, a transistor includes a gallium nitride (GaN) layer above a substrate, a gate structure over the GaN layer, a source region on a first side of the gate structure, a drain region on a second side of the gate structure, the second side opposite the first side, a source field plate above the source region, and a drain field plate above the drain region.
    Type: Application
    Filed: September 28, 2017
    Publication date: July 16, 2020
    Inventors: Han Wui THEN, Stephan LEUSCHNER, Marko RADOSAVLJEVIC, Sansaptak DASGUPTA