Abstract: RF front end systems or modules with an acoustic wave resonator (AWR) on an interposer substrate are described. In an example, an integrated system includes an active die, the active die comprising a semiconductor substrate having a plurality of active circuits therein. An interposer is also included, the interposer comprising an acoustic wave resonator (AWR). A seal frame couples the active die to the interposer, the seal frame surrounding the acoustic wave resonator and hermetically sealing the acoustic wave resonator between the active die and the interposer.

Abstract: A variable capacitance III-N device having multiple two-dimensional electron gas (2DEG) layers are described. In some embodiments, the device comprises a first source and a first drain; a first polarization layer adjacent to the first source and the first drain; a first channel layer coupled to the first source and the first drain and adjacent to the first polarization layer, the first channel layer comprising a first 2DEG region; a second source and a second drain; a second polarization layer adjacent to the second source and the second drain; and a second channel layer coupled to the second source and the second drain and adjacent to the second polarization layer, the second channel layer comprising a second 2DEG region, wherein the second channel layer is over the first polarization layer.

Abstract: A Group III-Nitride (III-N) device structure is provided comprising: a heterostructure having three or more layers comprising III-N material, an anode n+ region and a cathode comprising donor dopants, wherein the anode n+ region and the cathode are on the first layer of the heterostructure and wherein the anode n+ region and the cathode extend beyond the heterostructure, and an anode metal region within a recess that extends through two or more of the layers, wherein the anode metal region is in electrical contact with the first layer, wherein the anode metal region comprises a first width within the recess and a second width beyond the recess, and wherein the anode metal region is coupled with the anode n+ region. Other embodiments are also disclosed and claimed.

Abstract: Examples provide a wideband filter structure and apparatus, a radio transceiver, a mobile terminal, and a method for filtering a radio signal. The wideband filter structure (10) for a radio signal comprises a combination of at least one acoustic resonator (12) and at least one analog resonator (14). The acoustic resonator (12) is coupled to the analog resonator (14). The wideband filter structure (10) comprises a further component (16), which is coupled to the combination of the acoustic resonator (12) and the analog resonator (14).

Abstract: An apparatus for reducing a magnetic coupling between a first electronic circuit and a second electronic circuit is provided. The apparatus includes a conductor loop enclosing the first electronic circuit or the second electronic circuit, and a tuning element coupled to the conductor loop. The conductor loop and the tuning element form a resonant circuit, wherein the tuning element is configured to adjust a resonance frequency of the resonant circuit to a frequency related to a frequency of a signal processed by the second electronic circuit.

Abstract: An apparatus for reducing a magnetic coupling between a first electronic circuit and a second electronic circuit is provided. The apparatus includes a conductor loop enclosing the first electronic circuit or the second electronic circuit, and a tuning element coupled to the conductor loop. The conductor loop and the tuning element form a resonant circuit, wherein the tuning element is configured to adjust a resonance frequency of the resonant circuit to a frequency related to a frequency of a signal processed by the second electronic circuit.

Abstract: A communication matching network for multi-harmonic suppression includes a communication circuit configured to provide a signal. The communication matching network further includes a matching circuit configured to receive the signal from the communication circuit and suppress one or more harmonics of the received signal to generate a filtered signal, wherein the matching circuit includes a transformer comprising a first winding and a second winding, wherein the first winding includes a first inductance and the second winding includes a second inductance and wherein the matching network includes a harmonic trap including a third inductance such that the third inductance is located inside or within a physical layout of the first winding and/or the second winding. The communication matching network further includes a receiver circuit configured to receive the filtered signal from the matching circuit for further processing.

Abstract: A communication matching network for multi-harmonic suppression includes a communication circuit configured to provide a signal. The communication matching network further includes a matching circuit configured to receive the signal from the communication circuit and suppress one or more harmonics of the received signal to generate a filtered signal, wherein the matching circuit includes a transformer comprising a first winding and a second winding, wherein the first winding includes a first inductance and the second winding includes a second inductance and wherein the matching network includes a harmonic trap including a third inductance such that the third inductance is located inside or within a physical layout of the first winding and/or the second winding. The communication matching network further includes a receiver circuit configured to receive the filtered signal from the matching circuit for further processing.

Abstract: A transformer is provided. The transformer includes at least one first primary turn; at least one second primary turn; and a first secondary turn and a second secondary turn. The first secondary turn and the second secondary turn are arranged laterally between the at least one first primary turn and the at least one second primary turn. The first secondary turn and the second secondary turn are arranged one above the other.

Abstract: A communication matching network for multi-harmonic suppression includes a communication circuit configured to provide a signal. The communication matching network further includes a matching circuit configured to receive the signal from the communication circuit and suppress one or more harmonics of the received signal to generate a filtered signal, wherein the matching circuit includes a transformer comprising a first winding and a second winding, wherein the first winding includes a first inductance and the second winding includes a second inductance and wherein the matching network includes a harmonic trap including a third inductance such that the third inductance is located inside or within a physical layout of the first winding and/or the second winding. The communication matching network further includes a receiver circuit configured to receive the filtered signal from the matching circuit for further processing.

Abstract: A differential amplifier stage may include: a first transistor having a gate terminal; a second transistor having a gate terminal; and a voltage limiting circuit coupled to the gate terminals of the first and second transistors, wherein the voltage limiting circuit limits a gate voltage supplied to at least one of the gate terminals of the first and second transistors.

Abstract: A digital-to-analog converter circuit including a plurality of digital-to-analog converter cells is provided. A first digital-to-analog converter cell of the plurality of digital-to-analog converter cells includes a cell control module configured to provide alternatingly a first voltage and a second voltage to a first electrode of a capacitive element of the first digital-to-analog converter cell based on a digital input signal during a predefined time interval. A second digital-to-analog converter cell of the plurality of digital-to-analog converter cells includes a cell control module configured to provide a third voltage to a first electrode of a capacitive element of the second digital-to-analog converter cell during the predefined time interval.

Abstract: A digital-to-analog converter circuit including a plurality of digital-to-analog converter cells is provided. A first digital-to-analog converter cell of the plurality of digital-to-analog converter cells includes a cell control module configured to provide alternatingly a first voltage and a second voltage to a first electrode of a capacitive element of the first digital-to-analog converter cell based on a digital input signal during a predefined time interval. A second digital-to-analog converter cell of the plurality of digital-to-analog converter cells includes a cell control module configured to provide a third voltage to a first electrode of a capacitive element of the second digital-to-analog converter cell during the predefined time interval.

Abstract: A transformer is provided. The transformer includes at least one first primary turn; at least one second primary turn; and a first secondary turn and a second secondary turn. The first secondary turn and the second secondary turn are arranged laterally between the at least one first primary turn and the at least one second primary turn. The first secondary turn and the second secondary turn are arranged one above the other.

Abstract: A transmission arrangement is disclosed having an amplifier which is set up to amplify a transmission signal and to provide it as an amplified transmission signal in differential form, an analysis circuit for determining a property of the amplified transmission signal, and a differential feedback path which is set up to supply the amplified transmission signal to the analysis circuit in differential form.

Abstract: An amplifier includes a first lower active sub cell and a second lower active sub cell, each comprising an input terminal and an output terminal, wherein the input terminals of the lower active sub cells are connected to the amplifier input and the output terminals of the lower active sub cells are not shorted. Furthermore, the amplifier includes a first upper active sub cell and a second upper active sub cell, each including a biasing terminal, wherein the input terminals and the output terminals of the upper active sub cells are coupled between the output terminals of the lower active sub cells and the amplifier output. The amplifier includes a bias controller configured to provide a first biasing signal to the first upper active sub cell and a second biasing signal to the second upper active sub cell based on an output power of the output signal.

Abstract: In accordance with one exemplary embodiment, an electronic circuit is provided, wherein the electronic circuit comprises a first transistor and also a second transistor coupled in series with the first transistor. Furthermore, the electronic circuit comprises a capacitor, wherein a first terminal of the capacitor is coupled to a control terminal of the second transistor, and wherein a second terminal of the capacitor is coupled to an electrical potential which is dependent on a radio-frequency input signal of the electronic circuit.

Abstract: A transmission arrangement is disclosed having an amplifier which is set up to amplify a transmission signal and to provide it as an amplified transmission signal in differential form, an analysis circuit for determining a property of the amplified transmission signal, and a differential feedback path which is set up to supply the amplified transmission signal to the analysis circuit in differential form.

Abstract: A cascode circuit includes a first transistor and a second transistor. The first transistor and the second transistor are connected to make a cascode. In addition, the circuit has a block capacitance which is connected between a control terminal of the second transistor and a source terminal of the first transistor. In addition, the circuit has a feedback element which is connected between a drain terminal of the second transistor and a control terminal of the first transistor.

Abstract: A differential amplifier stage may include: a first transistor having a gate terminal; a second transistor having a gate terminal; and a voltage limiting circuit coupled to the gate terminals of the first and second transistors, wherein the voltage limiting circuit limits a gate voltage supplied to at least one of the gate terminals of the first and second transistors.