Abstract: A method of processing sheets of different formats, including feeding the sheets of different formats in a feeding direction one behind the other, and at a certain feeding speed, to at least two collecting drums, the at least two collecting drums each having cylindrical lateral surfaces, driving each of the at least two collecting drums about a respective axis of rotation at a circumferential speed, the circumferential speed corresponding to the feeding speed of the sheets, temporarily securing at least some of the sheets on one of the at least two collecting drums to form a sheet stack, detaching the sheet stack from the at least one of the at least two collecting drums, and bringing together the sheets or the sheet stack detached from the at least one of the at least two collecting drums with sheets or a sheet stack detached from another one.

Abstract: Sheets of different formats, i.e. of different format lengths, are transported in a feeding direction one behind the other; and at a certain conveying speed, to at least two collecting drums, which have essentially cylindrical lateral surfaces. Each of these collecting drums is driven about an axis of rotation at a circumferential speed, which corresponds essentially to the feeding speed of the sheets. The first incoming sheet is secured temporarily on one of the collecting drums, while the following, second sheet is secured temporarily on the other collecting drum. At a suitable point in time, the two sheets secured on the collecting drums are detached from the collecting drums and brought together with the third fed sheet to form a sub-product or end product.

Abstract: A technique comprising: producing a plurality of devices according to a common production process; and determining the thickness of a layer of one of said plurality of devices using an indicator of a first electrical property dependent on the area of overlap between a first element of the device and a second element of the device partially underlying said first element via said layer, wherein the method further comprises: additionally using an indicator of a second electrical property dependent on the area of overlap between said first element of the device and a third element of the device also partially underlying said first element via said layer, wherein (a) the difference between (i) a measured indicator of said first electrical property, and (ii) a measured indicator of said second electrical property provides a more reliable indicator of the thickness of said layer than (b) an indicator of said first electrical property.

Abstract: Sheets of different formats, i.e. of different format lengths, are transported in a feeding direction one behind the other; and at a certain conveying speed, to at least two collecting drums, which have essentially cylindrical lateral surfaces. Each of these collecting drums is driven about an axis of rotation at a circumferential speed, which corresponds essentially to the feeding speed of the sheets. The first incoming sheet is secured temporarily on one of the collecting drums, while the following, second sheet is secured temporarily on the other collecting drum. At a suitable point in time, the two sheets secured on the collecting drums are detached from the collecting drums and brought together with the third fed sheet to form a sub-product or end product.

Abstract: The present invention is a method, circuit and system for erasing a non-volatile memory cell. A shunting element (e.g. transistor) may be introduced and/or activated between bit-lines to which one or more NVM cells being erased are connected. The shunting element may be located and/or activated across two bit-lines defining a given column of cells, where one or a subset of cells from the column may be undergoing an erase operation or procedure. The shunting element may be located, and/or activated, at some distance from the two bit-lines defining the given column of cells, and the shunting element may be electrically connected to the bit-lines defining the column through select transistors and/or through global bit-lines.

Abstract: In an embodiment, an integrated circuit having a memory cell arrangement is provided. The memory cell arrangement may include a substrate, a fin structure disposed above the substrate, and a memory cell contacting region. The fin structure may include a memory cell region having a plurality of memory cell structures being disposed above one another, each memory cell structure having an active region of a respective memory cell. Furthermore, the memory cell contacting region may be configured to electrically contact each of the memory cell structures, wherein the memory cell contacting region may include a plurality of contact regions, which are at least partially displaced with respect to each other in a direction parallel to the main processing surface of the substrate.

Abstract: The bit lines are produced by an implantation of a dopant by means of a sacrificial hard mask layer, which is later replaced with the gate electrodes formed of polysilicon in the memory cell array. Striplike areas of the memory cell array, which run transversely to the bit lines, are reserved by a blocking layer to be occupied by the bit line contacts. In these areas, the hard mask is used to form contact holes, which are self-aligned with the implanted buried bit lines. Between the blocked areas, the word lines are arranged normally to the bit lines.

Abstract: In an embodiment, an integrated circuit having a memory cell arrangement is provided. The memory cell arrangement may include a substrate, a fin structure disposed above the substrate, and a memory cell contacting region. The fin structure may include a memory cell region having a plurality of memory cell structures being disposed above one another, each memory cell structure having an active region of a respective memory cell. Furthermore, the memory cell contacting region may be configured to electrically contact each of the memory cell structures, wherein the memory cell contacting region may include a plurality of contact regions, which are at least partially displaced with respect to each other in a direction parallel to the main processing surface of the substrate.

Abstract: A memory layer sequence comprising a lower confinement layer (2), a charge-trapping layer (3), and an upper confinement layer (4) is applied on the main surface of a silicon substrate (1). By a photolithography step, trenches running parallel at a distance from one another are etched to delimitate the active area. A trench filling (7) is applied by growth or deposition of dielectric material or by a selective oxidation of the substrate material. After the removal of the charge-trapping layer sequence in a peripheral area and the deposition of a gate dielectric material provided for the transistors of an addressing circuitry, wordline stacks (8) are formed.

Abstract: A semiconductor memory device includes a semiconductor substrate, first conductive lines, second conductive lines, and memory cells. The second conductive lines include doped regions within the substrate and have a ratio of depth to width that is greater than unity. A semiconductor structure comprises a semiconductor substrate, a doped region and a charge trapping region beneath and adjoining the doped region. A semiconductor memory device comprises a semiconductor substrate, first conductive lines, second conductive lines, charge trapping regions, and memory cells. The second conductive lines are formed as doped regions within the substrate, wherein the charge trapping regions are arranged beneath and adjoin respective doped regions. Methods of manufacturing a semiconductor structure and a semiconductor memory device are provided.

Abstract: Insulation regions in the manner of STI isolations, which run transversely with respect to the word lines, isolate the source/drain regions of adjacent memory cells. Metallic bit lines are applied on the top side and patterned for example along zigzag lines such that the source/drain regions of a memory transistor which are contact-connected by the bit lines are in each case electrically connected by two mutually adjacent bit lines.

Abstract: At least one memory layer is provided on a substrate surface. A plurality of parallel conductor strips is formed from electrically conductive material above the memory layer. Sidewalls of the conductor strips are provided with spacers of an electrically conductive material.

Abstract: A semiconductor device comprises a memory cell (160) including a transistor body (150) having a top surface (111) and including a first doping area (10a) and a second doping area (10b) with a channel region (110) in between. The memory cell (160) further includes a gate electrode (3a) arranged above the channel region (110) and separated therefrom by a dielectric layer (2a). An oxide-nitride-oxide layer (66) has first portions (661) and second portions (662). The first portions (661) of the oxide-nitride-oxide layer (66) are arranged above at least parts of the first and second doping areas (10a, 10b) and are substantially parallel to the top surface (111) of the transistor body (150). The second portions (662) of the oxide-nitride-oxide layer (66) are adjacent to the gate electrode (3a) and extend in a direction not substantially parallel to the top surface (111) of the transistor body (150).

Abstract: The bit lines are produced by an implantation of a dopant by means of a sacrificial hard mask layer, which is later replaced with the gate electrodes formed of polysilicon in the memory cell array. Striplike areas of the memory cell array, which run transversely to the bit lines, are reserved by a blocking layer to be occupied by the bit line contacts. In these areas, the hard mask is used to form contact holes, which are self-aligned with the implanted buried bit lines. Between the blocked areas, the word lines are arranged normally to the bit lines.

Abstract: The present invention is a method, circuit and system for erasing a non-volatile memory cell. A shunting element (e.g. transistor) may be introduced and/or activated between bit-lines to which one or more NVM cells being erased are connected. The shunting element may be located and/or activated across two bit-lines defining a given column of cells, where one or a subset of cells from the column may be undergoing an erase operation or procedure. The shunting element may be located, and/or activated, at some distance from the two bit-lines defining the given column of cells, and the shunting element may be electrically connected to the bit-lines defining the column through select transistors and/or through global bit-lines.

Abstract: A plurality of parallel shallow trenches is etched at a main surface of a semiconductor substrate. A sequence of dielectric materials that are suitable for charge-trapping is applied on the whole surface including sidewalls and bottom surfaces of the etched trenches. This layer sequence completely fills the trenches and forms the shallow trench isolations. An additional layer can be provided between the memory layer and the top layer in order to achieve a planar upper surface.

Abstract: A storage layer sequence (20) and gate electrodes (34) are arranged on a substrate (10). The gate electrodes (34) may be fabricated in a gate electrode layer (22) made of electrically conductively doped polysilicon. Apart from an optional barrier layer (45), the word lines are solely formed from a material having a low resistivity, preferably from a metal layer (46). Word line spacers (52) are arranged on sidewalls for the purpose of electrical insulation and as a barrier against outdiffusion of metal atoms.

Abstract: A memory layer sequence comprising a lower confinement layer (2), a charge-trapping layer (3), and an upper confinement layer (4) is applied on the main surface of a silicon substrate (1). By a photolithography step, trenches running parallel at a distance from one another are etched to delimitate the active area. A trench filling (7) is applied by growth or deposition of dielectric material or by a selective oxidation of the substrate material. After the removal of the charge-trapping layer sequence in a peripheral area and the deposition of a gate dielectric material provided for the transistors of an addressing circuitry, wordline stacks (8) are formed.

Abstract: A non-volatile semiconductor memory includes a substrate having a substrate region, at least one word line, a plurality of non-volatile memory cells arranged in a plurality of sectors and further comprising first wells of a first doping type, electrically insulating elements and switching elements. Each sector includes a plurality of non-volatile memory cells commonly arranged in a respective first well. The at least one word line electrically connecting memory cells of a group of sectors among the plurality of sectors. The first wells are separated from the substrate region and from each other by means of the electrically insulating elements. Each first well is connected to a respective switching element and the semiconductor memory is constructed such that each first well is biasable to a predetermined potential by means of the respective switching element. Further, a method is provided for operating the above non-volatile semiconductor memory.

Abstract: A non-volatile semiconductor memory includes a substrate having a substrate region, at least one word line, a plurality of non-volatile memory cells arranged in a plurality of sectors and further comprising first wells of a first doping type, electrically insulating elements and switching elements. Each sector comprises a plurality of non-volatile memory cells commonly arranged in a respective first well. The at least one word line electrically connecting memory cells of a group of sectors among the plurality of sectors. The first wells are separated from the substrate region and from each other by means of the electrically insulating elements. Each first well is connected to a respective switching element and the semiconductor memory is constructed such that each first well is biasable to a predetermined potential by means of the respective switching element. Further, a method is provided for operating the above non-volatile semiconductor memory.