Abstract: A method of dataset replica migration is described. An application session may start on a first compute node. A first replica of the dataset to be accessed by the application session may be located on a second compute node. A second replica of the dataset is created to be co-located with the first compute node. A first data block of the dataset may be requested by the application session. The first data block of the first replica of the dataset may be read from the second compute node, when the second replica does not have a copy of the first data block stored in the second replica. The retrieved first data block may be copied to the second replica. The first data block may be read from the second replica, when the first data block is requested by the application session and is contained in the second replica.

Abstract: A method of dataset replica migration is described. An application session may start on a first compute node. A first replica of the dataset to be accessed by the application session may be located on a second compute node. A second replica of the dataset is created to be co-located with the first compute node. A first data block of the dataset may be requested by the application session. The first data block of the first replica of the dataset may be read from the second compute node, when the second replica does not have a copy of the first data block stored in the second replica. The retrieved first data block may be copied to the second replica. The first data block may be read from the second replica, when the first data block is requested by the application session and is contained in the second replica.

Abstract: Embodiments relate to providing a data stream interface for offloading the inflation/deflation processing of data to a stateless compression accelerator. An aspect includes transmitting a request to inflate or deflate a data stream to a compression accelerator. The request may include references to an input buffer for storing input data from the data stream, an output buffer for storing processed input data, and a state data control block for storing a stream state. The stream state is provided to the compression accelerator to continue processing the data stream responsive to the request being a subsequent request. The compression accelerator is instructed to store a current stream state in the state data control block responsive to the request being a non-final request. Accordingly, the current stream state is received from the compression accelerator responsive to the request being a non-final request. The processed input data is received from the compression accelerator.

Abstract: Embodiments relate to providing a data stream interface for offloading the inflation/deflation processing of data to a stateless compression accelerator. An aspect includes transmitting a request to inflate or deflate a data stream to a compression accelerator. The request may include references to an input buffer for storing input data from the data stream, an output buffer for storing processed input data, and a state data control block for storing a stream state. The stream state is provided to the compression accelerator to continue processing the data stream responsive to the request being a subsequent request. The compression accelerator is instructed to store a current stream state in the state data control block responsive to the request being a non-final request. Accordingly, the current stream state is received from the compression accelerator responsive to the request being a non-final request. The processed input data is received from the compression accelerator.

Abstract: An output sequence of data elements is processed. The output sequence of data elements represents a sequence of input data elements in a compressed format. An output data element comprises a backward reference for each string in the input data elements that occurs again in an input data element that is used to produce the output data element. A backward reference identified in a selected output data element is used for selecting the string to which it refers in the stored input data elements. The selected string is combined with strings of one or more subsequent output data elements. A matching sequence in the stored input data elements matching at least part of one or more combined strings is found. A combined string of the one or more combined strings having the longest matching sequence is selected. The backward reference is redefined to indicate the longest matching sequence.

Abstract: Concurrently writing an uncompressed data element, if the uncompressed data element comprises an indication that it is valid, in a main hash table using a first address generated by a first hash function, and reading a first data element from the main hash table using the first address. Introducing a first pipeline delay for maintaining the uncompressed data element in a first data path until the first data element is read. Concurrently writing the first data element to a victim hash table, if the first data element comprises an indication that it is valid, using a second address generated by a second hash function, and reading a second data element from the victim hash table using a third address generated by the second hash function. Introducing a second pipeline delay for maintaining the uncompressed data element in the first data path until the second data element is read.

Abstract: A covering device for a luggage compartment of a vehicle substantially comprises a trunk covering comprising an inner roller blind which covers the luggage compartment. In order to install the trunk covering in, and remove the latter from, the vehicle, said trunk covering is brought by one end vertically and horizontally into a plug-in device on the vehicle, wherein the remote, other longitudinal end of the trunk covering is latched in a lock by means of a rotational movement.

Abstract: An approach is provided in which a hardware accelerator receives a request to decompress a data stream that includes multiple deflate blocks and multiple deflate elements compressed according to block-specific compression configuration information. The hardware accelerator identifies a commit point that is based upon an interruption of a first decompression session of the data stream and corresponds to one of the deflate blocks. As such, the hardware accelerator configures a decompression engine based upon the corresponding deflate block's configuration information and, in turn, recommences decompression of the data stream at an input bit location corresponding to the commit point.

Abstract: Embodiments relate to providing a data stream interface for offloading the inflation/deflation processing of data to a stateless compression accelerator. An aspect includes transmitting a request to inflate or deflate a data stream to a compression accelerator. The request may include references to an input buffer for storing input data from the data stream, an output buffer for storing processed input data, and a state data control block for storing a stream state. The stream state is provided to the compression accelerator to continue processing the data stream responsive to the request being a subsequent request. The compression accelerator is instructed to store a current stream state in the state data control block responsive to the request being a non-final request. Accordingly, the current stream state is received from the compression accelerator responsive to the request being a non-final request. The processed input data is received from the compression accelerator.

Abstract: Embodiments relate an address translation/specification (ATS) field. An aspect includes receiving a work queue entry from a work queue in a main memory by a hardware accelerator, the work queue entry corresponding to an operation of the hardware accelerator that is requested by user-space software, the work queue entry comprising a first ATS field that describes a structure of the work queue entry. Another aspect includes, based on determining that the first ATS field is consistent with the operation corresponding to the work queue entry and the structure of the work queue entry, executing the operation corresponding to the work queue entry by the hardware accelerator. Another aspect includes, based on determining that the first ATS field is not consistent with the operation corresponding to the work queue entry and the structure of the work queue entry, rejecting the work queue entry by the hardware accelerator.

Abstract: Embodiments relate an address translation/specification (ATS) field. An aspect includes receiving a work queue entry from a work queue in a main memory by a hardware accelerator, the work queue entry corresponding to an operation of the hardware accelerator that is requested by user-space software, the work queue entry comprising a first ATS field that describes a structure of the work queue entry. Another aspect includes, based on determining that the first ATS field is consistent with the operation corresponding to the work queue entry and the structure of the work queue entry, executing the operation corresponding to the work queue entry by the hardware accelerator. Another aspect includes, based on determining that the first ATS field is not consistent with the operation corresponding to the work queue entry and the structure of the work queue entry, rejecting the work queue entry by the hardware accelerator.

Abstract: A preprocessing unit includes a data receiver to receive a data packet containing packet information, application data, and application data information, a relevance checker to determine relevance of the data packet in dependence on the packet information, an output module to output preprocessor output data, and a first controller to control output of preprocessor output data in dependence on the relevance of the data packet. In order to discard redundant data, thereby reducing the load of the memory, bus, and CPU of the computer system, the preprocessing unit further comprises a redundancy checker to determine redundancy of the application data preferably and a second controller to control output of preprocessor output data in dependence on the redundancy of the application data.

Abstract: Mechanisms, in a processor chip, are provided for obtaining debug data from on-chip logic of the processor chip while the processor chip is in a secure mode of operation. The processor chip is placed into a secure mode of operation in which access to internal logic of the processor chip to control the internal logic of the processor chip, by mechanisms external to the processor chip, is disabled on a debug interface of the processor chip. A triggering condition of the processor chip is detected that is a trigger for initiated debug data collection from the on-chip logic. Debug data collection is performed from the on-chip logic to generate debug data. Data is output, by the processor chip to an external mechanism, on the debug interface based on the debug data.

Abstract: Embodiments relate to providing a data stream interface for offloading the inflation/deflation processing of data to a stateless compression accelerator. An aspect includes transmitting a request to inflate or deflate a data stream to a compression accelerator. The request may include references to an input buffer for storing input data from the data stream, an output buffer for storing processed input data, and a state data control block for storing a stream state. The stream state is provided to the compression accelerator to continue processing the data stream responsive to the request being a subsequent request. The compression accelerator is instructed to store a current stream state in the state data control block responsive to the request being a non-final request. Accordingly, the current stream state is received from the compression accelerator responsive to the request being a non-final request. The processed input data is received from the compression accelerator.

Abstract: A preprocessing unit includes a data receiver to receive a data packet containing packet information, application data, and application data information, a relevance checker to determine relevance of the data packet in dependence on the packet information, an output module to output preprocessor output data, and a first controller to control output of preprocessor output data in dependence on the relevance of the data packet. In order to discard redundant data, thereby reducing the load of the memory, bus, and CPU of the computer system, the preprocessing unit further comprises a redundancy checker to determine redundancy of the application data preferably and a second controller to control output of preprocessor output data in dependence on the redundancy of the application data.

Abstract: A covering device for a luggage compartment of a vehicle substantially comprises a trunk covering comprising an inner roller blind which covers the luggage compartment. In order to install the trunk covering in, and remove the latter from, the vehicle, said trunk covering is brought by one end vertically and horizontally into a plug-in device on the vehicle, wherein the remote, other longitudinal end of the trunk covering is latched in a lock by means of a rotational movement.

Abstract: Mechanisms, in a processor chip, are provided for obtaining debug data from on-chip logic of the processor chip while the processor chip is in a secure mode of operation. The processor chip is placed into a secure mode of operation in which access to internal logic of the processor chip to control the internal logic of the processor chip, by mechanisms external to the processor chip, is disabled on a debug interface of the processor chip. A triggering condition of the processor chip is detected that is a trigger for initiated debug data collection from the on-chip logic. Debug data collection is performed from the on-chip logic to generate debug data. Data is output, by the processor chip to an external mechanism, on the debug interface based on the debug data.

Abstract: Mechanisms, in a processor chip, are provided for obtaining debug data from on-chip logic of the processor chip while the processor chip is in a secure mode of operation. The processor chip is placed into a secure mode of operation in which access to internal logic of the processor chip to control the internal logic of the processor chip, by mechanisms external to the processor chip, is disabled on a debug interface of the processor chip. A triggering condition of the processor chip is detected that is a trigger for initiated debug data collection from the on-chip logic. Debug data collection is performed from the on-chip logic to generate debug data. Data is output, by the processor chip to an external mechanism, on the debug interface based on the debug data.

Abstract: A chain catcher device for bicycle chains, provided for preventing the bicycle chain from slipping off from an inner chain ring (34), comprises a fastening element (10) and a catching element (12). The fastening element serves for fastening the chain catcher device to the bicycle frame (24), particularly to fasteners for a bottle holder. For this purpose, the fastening element comprises two fastening means (14, 16; 18, 20) arranged at mutual distances on the fastening element.

Abstract: A method provides exception handling for a computer system. As an error in the computer system's hardware is detected, an exception vector pertaining to the hardware error is determined, and execution flow is transferred to a dispatcher that corresponds/pertains to the exception vector. A specific instance of a plurality of instances of a main exception handler is selected, and the specific instance of the main exception handler is executed. The actual exception handler thus contains two distinct parts, a dispatcher, which is unique and preferably resides in a safe memory region, and a main exception handler, multiple copies of which reside in an unsafe memory region.