Abstract: The invention relates to an assembly method to enable local electrical bonds between zones located on a face of a first substrate and corresponding zones located on a face of a second substrate, said faces being located facing each other, at least one of the substrates having a surface topography, characterised in that the method comprises steps consisting of: forming an intermediate layer comprising at least one burial layer on the face of the substrate or substrates having a surface topography to make it (them) compatible with molecular bonding of said faces of substrates to each other from a topographic point of view, the resistivity and/or thickness of the intermediate layer being chosen to enable said local electrical bonds, bringing the two faces into contact, the substrates being positioned so as to create electrical bonds between areas located on the first substrate and the corresponding areas located on the second substrate, bonding the faces of the first and second substrates by molecular bonding

Abstract: A process assembling first and second substrates on contact faces by molecular bonding. The first substrate contact face has an electrically conducting layer on at least part of its surface. The process deposits a bond layer on at least part of the electrically conducting layer, which bond layer can molecularly bond with a zone of the second substrate contact face and be combined with the electrically conducting layer to form a conducting alloy, contacts the bond layer with the zone of the second substrate contact face and molecularly bond them, and transforms over all or part of its thickness of all or part of the electrically conducting layer with all or part of the bond layer and with at least part of the thickness of the zone of the contact face on all or part of the surface of the second substrate to form a conducting alloy(s) zone.

Abstract: The invention relates to a sealing process for two wafers (2, 12) made of semiconducting materials, comprising: a step for implantation of metallic species (4) in at least the first wafer, a step for assembly of the first and second wafer, an annealing step.