Abstract: The invention proposes a lighting device, in particular an emergency lighting device. The lighting device includes a first housing (2), a lighting means (12), for example an LED arranged at the first housing (2) and an electronic circuitry accommodated in the first housing (2) for operating the lighting means (12). A second housing (3) of the lighting device accommodates an energy storage means (13) such as a rechargeable battery, wherein the first housing (2) and the second housing (3) are arranged spaced apart. An interconnecting means (4) mechanically connects the first housing (2) and the second housing (3) in an elastic manner and also connects electrically the electronic circuitry and the energy storage means (13). The interconnecting means (4) of the lighting device of a preferred embodiment comprises a cable which is overmoulded to provide compressive strength in an axial direction of the cable.

Abstract: An endotracheal intubation device has a flexible main tube having an outer end and a patient end for permitting passage of air from an environment outside a patient into a trachea of the patient when the patient is intubated with the device. An inflatable and deflatable balloon is attached to the main tube at a position closer to the patient end than the outer end of the main tube. The balloon is inflatable in the trachea to immobilize the main tube in the trachea. The balloon has a wall and the wall has a recess in a top surface thereof for collecting fluid secretions of the patient intubated with the device to prevent the fluid secretions from passing down the trachea into lungs when the balloon is deflated in the trachea. Preventing fluid from reaching the lungs when the device is removed reduces risk of ventilator associated pneumonia (VAP).

Abstract: The invention proposes a lighting device, in particular an emergency lighting device. The lighting device includes a first housing (2), a lighting means (12), for example an LED arranged at the first housing (2) and an electronic circuitry accommodated in the first housing (2) for operating the lighting means (12). A second housing (3) of the lighting device accommodates an energy storage means (13) such as a rechargeable battery, wherein the first housing (2) and the second housing (3) are arranged spaced apart. An interconnecting means (4) mechanically connects the first housing (2) and the second housing (3) in an elastic manner and also connects electrically the electronic circuitry and the energy storage means (13). The interconnecting means (4) of the lighting device of a preferred embodiment comprises a cable which is overmoulded to provide compressive strength in an axial direction of the cable.

Abstract: The invention relates to an operating device (10) for at least one light-emitting diode (9) having an input (11) for coupling to a DC bus (6) in order to receive a DC supply voltage. The operating device (10) has a configurable emergency light function. The operating device (10) is designed to produce, in the emergency light case, the LED currently for the at least one light-emitting diode (9) in dependence on how the emergency light function is configured.

Abstract: The invention relates to an operating device (10) for at least one light-emitting diode (9) having an input (11) for coupling to a DC bus (6) in order to receive a DC supply voltage. The operating device (10) has a configurable emergency light function. The operating device (10) is designed to produce, in the emergency light case, the LED currently for the at least one light-emitting diode (9) in dependence on how the emergency light function is configured.

Abstract: A high quality imager is constructed using a silicon-on-insulator (SOI) process with sensors fabricated in the SOI substrate and isolated by the buried oxide (BOX) from associated readout circuitry in the SOI layer. Handle windows are opened in the SOI device layer for fabrication of the sensors in the handle layer substrate and then closed prior to processing in the device layer. By keeping the buried oxide layer intact, the described technique allows for independent processing of sensors and readout circuitry so that each is optimized with regard to thermal and dopant properties without concern for degradation of the other. The process is compatible with the fabrication of readout circuitry using transistors having independent double-gates, which offer simultaneous advantages in scalability, low power and low noise. Photodiode sensors are shown with allowance for many other types of sensors. The process easily accommodates hardening against radiation.

Abstract: Memory cells are constructed from double-gated four terminal transistors having independent gate control. DRAM cells may use one, two or three transistors. Single transistor cells are constructed either with or without a bit storage capacitor, and both NAND- and NOR-type Non-Volatile NVRAM cells, as well as Ferroelectric FeRAM cells, are described. For all cells, top gates provide conventional access while independent bottom gates provide control to optimize memory retention for given speed and power parameters as well as to accommodate hardening against radiation. In a single transistor cell without a capacitor, use of the bottom gate allows packing to a density approaching 2 F2. Using a ferroelectric material as the gate insulator produces a single-transistor FeRAM cell that overcomes the industry-wide Write Disturb problem. The memory cells are compatible with SOI logic circuitry for use as embedded RAM in SOC applications.

Abstract: A family of logic circuits is constructed from double-gated four terminal transistors having independent gate control. First and second inputs to each logic element are independently coupled to the top and bottom gates of a transistor. The output voltage developed at either the source or drain represents an output logic state value according to the designed logic element. In a dynamic configuration the drain is precharged to an appropriate voltage. Complementary static CMOS configurations are also shown. Bottom Gates not driven by logic inputs or control signals may be biased to control the speed and power of the described logic circuits. Specific designs are given for AND, NAND, XOR, XNOR, OR and NOR combinational logic elements.

Abstract: This independent double-gated transistor architecture creates a MOSFET, JFET or MESFET in parallel with a JFET. Its two gates may be configured to provide a four-terminal device for independent gate control, a floating gate device, and a double-gate device. First and second insulating spacers are disposed on opposing sides of the top gate with the first spacer between the source and the top gate and the second spacer between the drain and the top gate. Source and drain extensions extend proximate to the spacers and couple to the channel. The spacers shield the channel from the field effect of the source and drain and further resist compression of the channel by the source and drain. Truly independent control of the two gates makes possible many 2-, 3- and 4-terminal device configurations that may be dynamically reconfigured to trade off speed against power. The resulting transistors exhibit inherent radiation tolerance.

Abstract: Memory cells are constructed from double-gated four terminal transistors having independent gate control. DRAM cells may use one, two or three transistors. Single transistor cells are constructed either with or without a bit storage capacitor, and both NAND- and NOR-type Non-Volatile NVRAM cells, as well as Ferroelectric FeRAM cells, are described. For all cells, top gates provide conventional access while independent bottom gates provide control to optimize memory retention for given speed and power parameters as well as to accommodate hardening against radiation. In a single transistor cell without a capacitor, use of the bottom gate allows packing to a density approaching 2 F2. Using a ferroelectric material as the gate insulator produces a single-transistor FeRAM cell that overcomes the industry-wide Write Disturb problem. The memory cells are compatible with SOI logic circuitry for use as embedded RAM in SOC applications.

Abstract: An OR gate circuit includes double-gated four terminal transistor with independent gate control. First and second inputs are independently coupled to the top and bottom gates of the transistor. The drain is coupled to an output and precharged to a low voltage. An input to either the top or bottom gates results in a high voltage to the drain and an output value of 1.

Abstract: An OR gate circuit includes double-gated four terminal transistor with independent gate control. First and second inputs are independently coupled to the top and bottom gates of the transistor. The drain is coupled to an output and precharged to a low voltage. An input to either the top or bottom gates results in a high voltage to the drain and an output value of 1.

Abstract: An OR gate circuit includes double-gated four terminal transistor with independent gate control. First and second inputs are independently coupled to the top and bottom gates of the transistor. The drain is coupled to an output and precharged to a low voltage. An input to either the top or bottom gates results in a high voltage to the drain and an output value of 1.

Abstract: A double-gated transistor architecture provides a four terminal device for independent gate control, a floating body device, and a dynamic threshold device. The channel may have a U-shaped cross-sectional area to increase the channel length and gate control. First and second insulating spacers are disposed on opposing sides of the top gate such that the first spacer is between the source and the top gate and the second spacer is between the drain and the top gate. The source and drain include extensions that extend proximate to the spacers and couple to the channel. The spacers shield the channel from the field effect of the source and drain and further resist compression of the channel by the source and drain.

Abstract: A SRAM cell includes double-gated PMOS and NMOS transistors to form a latch and retain a value. The unique MOSFET transistor architecture provides a four terminal device for independent gate control, a floating body device, and a dynamic threshold device. The channel may have a U-shaped cross-sectional area to increase the channel length and gate control. First and second insulating spacers are disposed on opposing sides of the top gate such that the first spacer is between the source and the top gate, and the second spacer is between the drain and the top gate. The source and drain include extensions that extend proximate to the spacers and couple to the channel. The spacers shield the channel from the field effect of the source and drain, and further resist compression of the channel by the source and drain.

Abstract: A double-gated transistor architecture provides a four terminal device for independent gate control, a floating body device, and a dynamic threshold device. The channel may have a U-shaped cross-sectional area to increase the channel length and gate control. First and second insulating spacers are disposed on opposing sides of the top gate such that the first spacer is between the source and the top gate and the second spacer is between the drain and the top gate. The source and drain include extensions that extend proximate to the spacers and couple to the channel. The spacers shield the channel from the field effect of the source and drain and further resist compression of the channel by the source and drain.

Abstract: A SRAM cell includes double-gated PMOS and NMOS transistors to form a latch and retain a value. The unique MOSFET transistor architecture provides a four terminal device for independent gate control, a floating body device, and a dynamic threshold device. The channel may have a U-shaped cross-sectional area to increase the channel length and gate control. First and second insulating spacers are disposed on opposing sides of the top gate such that the first spacer is between the source and the top gate, and the second spacer is between the drain and the top gate. The source and drain include extensions that extend proximate to the spacers and couple to the channel. The spacers shield the channel from the field effect of the source and drain, and further resist compression of the channel by the source and drain.

Abstract: An OR gate circuit includes double-gated four terminal transistor with independent gate control. First and second inputs are independently coupled to the top and bottom gates of the transistor. The drain is coupled to an output and precharged to a low voltage. An input to either the top or bottom gates results in a high voltage to the drain and an output value of 1.

Abstract: This invention provides the structure and fabrication process of a completely planar, Damascene double gated transistor. The structure has a novel self-aligned, hyper-abrupt retrograde body and a zero-parasitic, endwall gate-body connection. The structure provides for increased density and enables ultra low power to be utilized. The methods also provide for simultaneously making both four-terminal and dynamic threshold MOSFET devices.

Abstract: This invention provides the structure and fabrication process of a completely planar, Damascene double gated transistor. The structure has a novel self-aligned, hyper-abrupt retrograde body and a zero-parasitic, endwall gate-body connection. The structure provides for increased density and enables ultra low power to be utilized. The methods also provide for simultaneously making both four-terminal and dynamic threshold MOSFET devices.