Abstract: A calibrated temperature sensor includes a power on oscillator responsive to a calibration enable signal for providing a power on clock signal, a temperature dependent oscillator responsive to said calibration enable signal for providing a temperature dependent clock signal, and a measurement logic circuit. The measurement logic circuit counts a first number of pulses of the temperature dependent clock signal during a first calibration period using the power on clock signal, a second number of pulses of the temperature dependent clock signal during a second calibration period using a system clock signal, and a third number of pulses of the power on clock signal over a third calibration period using the system clock signal, and a fourth number of pulses of the temperature dependent clock signal using the system clock signal during a normal operation mode, wherein the first calibration period precedes both the second and third calibration periods.

Abstract: A calibrated temperature sensor includes a power on oscillator responsive to a calibration enable signal for providing a power on clock signal, a temperature dependent oscillator responsive to said calibration enable signal for providing a temperature dependent clock signal, and a measurement logic circuit. The measurement logic circuit counts a first number of pulses of the temperature dependent clock signal during a first calibration period using the power on clock signal, a second number of pulses of the temperature dependent clock signal during a second calibration period using a system clock signal, and a third number of pulses of the power on clock signal over a third calibration period using the system clock signal, and a fourth number of pulses of the temperature dependent clock signal using the system clock signal during a normal operation mode, wherein the first calibration period precedes both the second and third calibration periods.

Abstract: Techniques are disclosed relating to controlling power consumption of temperature sensors in integrated circuits. In one embodiment, an integrated circuit is disclosed that includes a temperature sensor that is configured to determine a temperature of the integrated circuit. The integrated circuit also includes a sensor controller that is configured to vary power consumption of the temperature sensor based, at least in part, on the determined temperature. In some embodiments, the integrated circuit may determine a sampling rate of the temperature sensor based, at least in part, on the determined temperature and a temperature threshold of the integrated circuit. The integrated circuit may then vary the power consumption of the temperature sensor by periodically disabling the temperature sensor based on the determined sampling rate.

Abstract: Information of a first type is determined at an integrated circuit die of a data processing device included an integrated circuit package. The integrated circuit package includes the first integrated circuit die and a second integrated circuit die. Information of a second type is determined at the integrated circuit die. The first and second type of information is transmitted from the integrated circuit die to another integrated circuit die using a time-divided multiplexed protocol by transmitting the first information during a first time slot of the protocol and transmitting the second information during a second time slot of the protocol.

Abstract: Techniques are disclosed relating to controlling power consumption of temperature sensors in integrated circuits. In one embodiment, an integrated circuit is disclosed that includes a temperature sensor that is configured to determine a temperature of the integrated circuit. The integrated circuit also includes a sensor controller that is configured to vary power consumption of the temperature sensor based, at least in part, on the determined temperature. In some embodiments, the integrated circuit may determine a sampling rate of the temperature sensor based, at least in part, on the determined temperature and a temperature threshold of the integrated circuit. The integrated circuit may then vary the power consumption of the temperature sensor by periodically disabling the temperature sensor based on the determined sampling rate.

Abstract: In one embodiment, a node comprises a plurality of processor cores and a node controller configured to receive a first read operation addressing a first register. The node controller is configured to return a first value in response to the first read operation, dependent on which processor core transmitted the first read operation. In another embodiment, the node comprises the processor cores and the node controller. The node controller comprises a queue shared by the processor cores. The processor cores are configured to transmit communications at a maximum rate of one every N clock cycles, where N is an integer equal to a number of the processor cores. In still another embodiment, a node comprises the processor cores and a plurality of fuses shared by the processor cores. In some embodiments, the node components are integrated onto a single integrated circuit chip (e.g. a chip multiprocessor).

Abstract: In one embodiment, a node comprises a plurality of processor cores and a node controller configured to receive a first read operation addressing a first register. The node controller is configured to return a first value in response to the first read operation, dependent on which processor core transmitted the first read operation. In another embodiment, the node comprises the processor cores and the node controller. The node controller comprises a queue shared by the processor cores. The processor cores are configured to transmit communications at a maximum rate of one every N clock cycles, where N is an integer equal to a number of the processor cores. In still another embodiment, a node comprises the processor cores and a plurality of fuses shared by the processor cores. In some embodiments, the node components are integrated onto a single integrated circuit chip (e.g. a chip multiprocessor).

Abstract: In one embodiment, a node comprises a plurality of processor cores and a node controller configured to receive a first read operation addressing a first register. The node controller is configured to return a first value in response to the first read operation, dependent on which processor core transmitted the first read operation. In another embodiment, the node comprises the processor cores and the node controller. The node controller comprises a queue shared by the processor cores. The processor cores are configured to transmit communications at a maximum rate of one every N clock cycles, where N is an integer equal to a number of the processor cores. In still another embodiment, a node comprises the processor cores and a plurality of fuses shared by the processor cores. In some embodiments, the node components are integrated onto a single integrated circuit chip (e.g. a chip multiprocessor).

Abstract: Information of a first type is determined at an integrated circuit die of a data processing device included an integrated circuit package. The integrated circuit package includes the first integrated circuit die and a second integrated circuit die. Information of a second type is determined at the integrated circuit die. The first and second type of information is transmitted from the integrated circuit die to another integrated circuit die using a time-divided multiplexed protocol by transmitting the first information during a first time slot of the protocol and transmitting the second information during a second time slot of the protocol.

Abstract: In one embodiment, a node comprises a plurality of processor cores and a node controller configured to receive a first read operation addressing a first register. The node controller is configured to return a first value in response to the first read operation, dependent on which processor core transmitted the first read operation. In another embodiment, the node comprises the processor cores and the node controller. The node controller comprises a queue shared by the processor cores. The processor cores are configured to transmit communications at a maximum rate of one every N clock cycles, where N is an integer equal to a number of the processor cores. In still another embodiment, a node comprises the processor cores and a plurality of fuses shared by the processor cores. In some embodiments, the node components are integrated onto a single integrated circuit chip (e.g. a chip multiprocessor).

Abstract: In one embodiment, a node comprises a plurality of processor cores and a node controller configured to receive a first read operation addressing a first register. The node controller is configured to return a first value in response to the first read operation, dependent on which processor core transmitted the first read operation. In another embodiment, the node comprises the processor cores and the node controller. The node controller comprises a queue shared by the processor cores. The processor cores are configured to transmit communications at a maximum rate of one every N clock cycles, where N is an integer equal to a number of the processor cores. In still another embodiment, a node comprises the processor cores and a plurality of fuses shared by the processor cores. In some embodiments, the node components are integrated onto a single integrated circuit chip (e.g. a chip multiprocessor).

Abstract: A tunnel device for an input/output node of a computer system. A tunnel device includes a first interface, a second interface and a control unit. The first interface may receive a plurality of data bytes associated with a command packet on a first external input/output bus. The second interface may be coupled to the first interface by an internal data path configured to convey up to a maximum number of data bytes in a given cycle. The control unit may be coupled to control the conveyance of the data bytes from the first interface to the second interface upon the internal data path. The first interface may further align the smaller number of data bytes on a corresponding number of designated bits of the internal data path with no intervening invalid data bytes when conveying a smaller number of data bytes than the maximum number of data bytes.

Abstract: A virtual channel buffer of a transaction scheduler in a computer system I/O node. A control unit includes a plurality of scheduler units. Each scheduler unit may include a first and a second buffer circuit. The first buffer circuit may include a first plurality of buffers and the second buffer circuit may include a second plurality of buffers, each of which are coupled to receive control commands from a first and second source, respectively. Each buffer of the first and the second plurality of buffers corresponds to a respective virtual channel of a plurality of virtual channels and may be configured for storing selected control commands that belong to said respective virtual channels. Each scheduler unit may also include an arbitration unit for arbitrating between the control commands stored in the first buffer circuit and the control commands stored in the second buffer circuit.

Abstract: A starvation avoidance mechanism for an input/output node of a computer system. A scheduler unit includes a first buffer circuit and a second buffer circuit. The first buffer circuit includes a first plurality of buffers for storing selected control commands received from a first source and the second buffer circuit includes a second plurality of buffers for storing selected control commands received from a second source. The scheduler further includes an arbitration circuit coupled to the first buffer circuit and to the second buffer circuit. The arbitration circuit may be configured to arbitrate between the control commands stored in the first buffer circuit and the control commands stored in the second buffer circuit. The outcome of selected arbitration cycles may be dependent upon a number of times in which a control command from a given one of the buffers is blocked due to an unavailable destination.

Abstract: A computer system I/O node. An input/output node for a computer system includes a first receiver unit configured to receive a first command on a first communication path and a first transmitter unit coupled to transmit a first corresponding command that corresponds to the first command on a second communication path. The input/output node also includes a second receiver unit configured to receive a second command on a third communication path and a second transmitter unit coupled to transmit a second corresponding command that corresponds to the second command on a fourth communication path. Further, the input/output node includes a bridge unit coupled to receive selected commands from the first receiver and the second receiver and configured to transmit commands corresponding to the selected commands upon a peripheral bus.

Abstract: A tagging and arbitration mechanism in an input/output node of a computer system. A mechanism for tagging commands in an input/output node of a computer system includes a tag circuit configured to receive a plurality of control commands. The tag circuit may also be configured to generate a tag value for each of the control commands. The tagging mechanism may also include a buffer circuit which is coupled to the tag circuit. The buffer circuit may include a plurality of buffers each corresponding to a respective virtual channel of a plurality of virtual channels for storing selected control commands that belong to the respective virtual channel. Further the tagging mechanism may include an arbitration circuit that is coupled to the buffer circuit and is configured to arbitrate between the plurality of buffers depending upon the tag value for each of the control commands.

Abstract: An arbitration mechanism for an input/output node of a computer system. An arbitration mechanism includes a buffer circuit for storing received control commands corresponding to a posted virtual channel and a second virtual channel. Each of the control commands includes an identifier value indicative of the source of the control command. A tag circuit that may generate a tag value for each of the control commands prior to the control commands being stored. The tag value may be indicative of an order of receipt of each of the control commands relative to other control commands and may be dependent upon the identifier value. In addition, an arbitration circuit may arbitrate between control commands stored within the buffer circuit dependent upon the tag value of each of the control commands. The arbitration circuit may select, independently of the tag values, a given control command and having a flag bit set.

Abstract: A virtual channel buffer bypass in a computer system input/output node. A control unit of an input/output node for a computer system includes a buffer circuit configured to receive control commands. The buffer circuit may include a plurality of buffers each corresponding to a respective virtual channel of a plurality of virtual channels for storing selected control commands that belong to the respective virtual channel. The buffer circuit may also be configured to determine whether each of the plurality of buffers is empty prior to storing a particular control command corresponding to a given one of the plurality of buffers. In addition, the buffer circuit may be configured to cause the particular control command to bypass the given one of the plurality of buffers in response to determining that each of the plurality of buffers is empty.

Abstract: A method and apparatus for combined transaction reordering and buffer management. The apparatus may include a buffer, a first generator circuit and a second generator circuit. The buffer is configured to store memory transaction responses received from a memory controller in a plurality of addressable locations. The first generator circuit is configured to generate a first memory transaction request encoded with a first tag corresponding to an address in the buffer in response to receiving a first memory request. The second generator circuit is configured to generate a second tag using the size of said first memory request added to the first tag. The first generator circuit may be further configured to generate a second memory transaction request encoded with the second tag corresponding to a second address in the buffer in response to receiving a second memory request successive to the first memory request.

Abstract: A starvation avoidance mechanism for an input/output node of a computer system. A scheduler unit includes a first buffer circuit and a second buffer circuit. The first buffer circuit includes a first plurality of buffers for storing selected control commands received from a first source and the second buffer circuit includes a second plurality of buffers for storing selected control commands received from a second source. The scheduler further includes an arbitration circuit coupled to the first buffer circuit and to the second buffer circuit. The arbitration circuit may be configured to arbitrate between the control commands stored in the first buffer circuit and the control commands stored in the second buffer circuit. The outcome of selected arbitration cycles may be dependent upon a number of times in which a control command from a given one of the buffers is blocked due to an unavailable destination.