Patents by Inventor Stephen C. Ennis

Stephen C. Ennis has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20030097500
    Abstract: A tagging and arbitration mechanism in an input/output node of a computer system. A mechanism for tagging commands in an input/output node of a computer system includes a tag circuit configured to receive a plurality of control commands. The tag circuit may also be configured to generate a tag value for each of the control commands. The tagging mechanism may also include a buffer circuit which is coupled to the tag circuit. The buffer circuit may include a plurality of buffers each corresponding to a respective virtual channel of a plurality of virtual channels for storing selected control commands that belong to the respective virtual channel. Further the tagging mechanism may include an arbitration circuit that is coupled to the buffer circuit and is configured to arbitrate between the plurality of buffers depending upon the tag value for each of the control commands.
    Type: Application
    Filed: October 15, 2001
    Publication date: May 22, 2003
    Inventor: Stephen C. Ennis
  • Publication number: 20030097499
    Abstract: A starvation avoidance mechanism for an input/output node of a computer system. A scheduler unit includes a first buffer circuit and a second buffer circuit. The first buffer circuit includes a first plurality of buffers for storing selected control commands received from a first source and the second buffer circuit includes a second plurality of buffers for storing selected control commands received from a second source. The scheduler further includes an arbitration circuit coupled to the first buffer circuit and to the second buffer circuit. The arbitration circuit may be configured to arbitrate between the control commands stored in the first buffer circuit and the control commands stored in the second buffer circuit. The outcome of selected arbitration cycles may be dependent upon a number of times in which a control command from a given one of the buffers is blocked due to an unavailable destination.
    Type: Application
    Filed: October 15, 2001
    Publication date: May 22, 2003
    Inventor: Stephen C. Ennis
  • Publication number: 20030093593
    Abstract: A virtual channel buffer bypass in a computer system input/output node. A control unit of an input/output node for a computer system includes a buffer circuit configured to receive control commands. The buffer circuit may include a plurality of buffers each corresponding to a respective virtual channel of a plurality of virtual channels for storing selected control commands that belong to the respective virtual channel. The buffer circuit may also be configured to determine whether each of the plurality of buffers is empty prior to storing a particular control command corresponding to a given one of the plurality of buffers. In addition, the buffer circuit may be configured to cause the particular control command to bypass the given one of the plurality of buffers in response to determining that each of the plurality of buffers is empty.
    Type: Application
    Filed: October 15, 2001
    Publication date: May 15, 2003
    Inventor: Stephen C. Ennis